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Message-Id: <20240511-mips-clks-v1-1-ddb4a10ee9f9@flygoat.com> Date: Sat, 11 May 2024 17:00:08 +0100 From: Jiaxun Yang <jiaxun.yang@...goat.com> To: Thomas Bogendoerfer <tsbogend@...ha.franken.de>, Serge Semin <fancer.lancer@...il.com>, Daniel Lezcano <daniel.lezcano@...aro.org>, Thomas Gleixner <tglx@...utronix.de> Cc: linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org, Jiaxun Yang <jiaxun.yang@...goat.com> Subject: [PATCH 1/7] MIPS: csrc-r4k: Refine rating computation Increase frequency addend dividend to 100000000 (10MHz) to reasonably accommodate multi GHz level mips_hpt_frequency. Cap rating of csrc-r4k into 299 to ensure it doesn't go into "Desired" range, given all the drama we have with CP0 count registers (SMP sync, behaviour on wait etc). Signed-off-by: Jiaxun Yang <jiaxun.yang@...goat.com> --- arch/mips/kernel/csrc-r4k.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index edc4afc080fa..262896871351 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -111,7 +111,8 @@ int __init init_r4k_clocksource(void) return -ENXIO; /* Calculate a somewhat reasonable rating value */ - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; + clocksource_mips.rating = 200; + clocksource_mips.rating += clamp(mips_hpt_frequency / 100000000, 0, 99); /* * R2 onwards makes the count accessible to user mode so it can be used -- 2.34.1
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