lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Date: Sat, 11 May 2024 14:25:53 -0300
From: Arnaldo Carvalho de Melo <acme@...nel.org>
To: Ian Rogers <irogers@...gle.com>
Cc: Breno Leitao <leitao@...ian.org>, Peter Zijlstra <peterz@...radead.org>,
	Ingo Molnar <mingo@...hat.com>, Namhyung Kim <namhyung@...nel.org>,
	Mark Rutland <mark.rutland@....com>,
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Jiri Olsa <jolsa@...nel.org>,
	Adrian Hunter <adrian.hunter@...el.com>, leit@...a.com,
	"open list:PERFORMANCE EVENTS SUBSYSTEM" <linux-perf-users@...r.kernel.org>,
	"open list:PERFORMANCE EVENTS SUBSYSTEM" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] perf list: Fix the --no-desc option

On Sat, May 11, 2024 at 09:11:00AM -0700, Ian Rogers wrote:
>    On Sat, May 11, 2024, 9:00 AM Arnaldo Carvalho de Melo
>    <[1]acme@...nel.org> wrote:
> 
>      On Wed, May 08, 2024 at 06:35:17AM -0700, Breno Leitao wrote:
>      > Currently, the --no-desc option in perf list isn't functioning as
>      > intended.
>      >
>      > This issue arises from the overwriting of struct option->desc with
>      the
>      > opposite value of struct option->long_desc. Consequently, whatever
>      > parse_options() returns at struct option->desc gets overridden
>      later,
>      > rendering the --desc or --no-desc arguments ineffective.
>      >
>      > To resolve this, set ->desc as true by default and allow
>      parse_options()
>      > to adjust it accordingly. This adjustment will fix the --no-desc
>      > option while preserving the functionality of the other parameters.
> 
>      Thanks, applied to perf-tools-next, and added this:
> 
>          Committer testing:
> 
>          Before:
> 
>            $ perf list --no-desc
>            <SNIP>
>            cache:
>              longest_lat_cache.miss
>                   [Counts the number of cacheable memory requests that
>      miss in the LLC. Counts on a per core basis. Unit: cpu_atom]
>              longest_lat_cache.reference
>                   [Counts the number of cacheable memory requests that
>      access the LLC. Counts on a per core basis. Unit: cpu_atom]
>              mem_bound_stalls.ifetch
>                   [Counts the number of cycles the core is stalled due to
>      an instruction cache or TLB miss which hit in the L2,LLC,DRAM or
>      MMIO (Non-DRAM). Unit: cpu_atom]
>              mem_bound_stalls.ifetch_dram_hit
>                   [Counts the number of cycles the core is stalled due to
>      an instruction cache or TLB miss which hit in DRAM or MMIO
>      (Non-DRAM). Unit: cpu_atom]
>              mem_bound_stalls.ifetch_l2_hit
>                   [Counts the number of cycles the core is stalled due to
>      an instruction cache or TLB miss which hit in the L2 cache. Unit:
>      cpu_atom]
>              mem_bound_stalls.ifetch_llc_hit
>                   [Counts the number of cycles the core is stalled due to
>      an instruction cache or TLB miss which hit in the LLC or other core
>      with HITE/F/M. Unit: cpu_atom]
>            <SNIP>
> 
>          After:
> 
>            $ perf list --no-desc
>            <SNIP>
>              cache:
>              longest_lat_cache.miss
>              longest_lat_cache.reference
>              mem_bound_stalls.ifetch
>              mem_bound_stalls.ifetch_dram_hit
>              mem_bound_stalls.ifetch_l2_hit
>              mem_bound_stalls.ifetch_llc_hit
>            <SNIP>
> 
>          Signed-off-by: Breno Leitao <[2]leitao@...ian.org>
>          Tested-by: Arnaldo Carvalho de Melo <[3]acme@...hat.com>
> 
>      - Arnaldo
> 
>      > Signed-off-by: Breno Leitao <[4]leitao@...ian.org>
>      > ---
>      >  tools/perf/builtin-list.c | 2 +-
>      >  1 file changed, 1 insertion(+), 1 deletion(-)
>      >
>      > diff --git a/tools/perf/builtin-list.c b/tools/perf/builtin-list.c
>      > index 02bf608d585e..58589f67e800 100644
>      > --- a/tools/perf/builtin-list.c
>      > +++ b/tools/perf/builtin-list.c
>      > @@ -491,6 +491,7 @@ int cmd_list(int argc, const char **argv)
>      >       int i, ret = 0;
>      >       struct print_state default_ps = {
>      >               .fp = stdout,
>      > +             .desc = true,
>      >       };
>      >       struct print_state json_ps = {
>      >               .fp = stdout,
>      > @@ -563,7 +564,6 @@ int cmd_list(int argc, const char **argv)
>      >               };
>      >               ps = &json_ps;
>      >       } else {
>      > -             default_ps.desc = !default_ps.long_desc;
> 
>    Given this, did you test the long description behavior?

So, without the patch:

perf list
<SNIP>
cache:
  longest_lat_cache.miss
       [Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis. Unit: cpu_atom]
<SNIP>

perf list --long-desc
<SNIP>
cache:
  longest_lat_cache.miss
       [Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads,reads for ownership (RFO),instruction fetches and L1 HW
        prefetches. If the platform has an L3 cache,the LLC is the L3 cache,otherwise it is the L2 cache. Counts on a per core basis]
<SNIP>

perf list --no-desc
<SNIP>
cache:
  longest_lat_cache.miss
       [Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis. Unit: cpu_atom]
<SNIP>

With Breno's patch the default doesn't change, --no-desc gets fixed but
--long-desc is broken:

perf list --long-desc
<SNIP>
cache:
  longest_lat_cache.miss
       [Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis. Unit: cpu_atom]
       [Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads,reads for ownership (RFO),instruction fetches and L1 HW
        prefetches. If the platform has an L3 cache,the LLC is the L3 cache,otherwise it is the L2 cache. Counts on a per core basis]
<SNIP>

Thanks for asking the question, I'm dropping the patch, Breno, can you
try again?

- Arnaldo

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ