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Message-ID: <20240513212535.rql55fdrvy2mdsrl@CAB-WSD-L081021>
Date: Tue, 14 May 2024 00:25:35 +0300
From: Dmitry Rokosov <ddrokosov@...utedevices.com>
To: Jerome Brunet <jbrunet@...libre.com>
CC: <neil.armstrong@...aro.org>, <mturquette@...libre.com>,
<sboyd@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <khilman@...libre.com>,
<martin.blumenstingl@...glemail.com>, <jian.hu@...ogic.com>,
<kernel@...rdevices.ru>, <rockosov@...il.com>,
<linux-amlogic@...ts.infradead.org>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2 3/7] clk: meson: a1: pll: support 'syspll'
general-purpose PLL for CPU clock
On Mon, May 13, 2024 at 02:48:58PM +0200, Jerome Brunet wrote:
>
> On Fri 10 May 2024 at 12:08, Dmitry Rokosov <ddrokosov@...utedevices.com> wrote:
>
> > The 'syspll' PLL, also known as the system PLL, is a general and
> > essential PLL responsible for generating the CPU clock frequency.
> > With its wide-ranging capabilities, it is designed to accommodate
> > frequencies within the range of 768MHz to 1536MHz.
> >
> > Signed-off-by: Dmitry Rokosov <ddrokosov@...utedevices.com>
> > ---
> > drivers/clk/meson/a1-pll.c | 79 ++++++++++++++++++++++++++++++++++++++
> > drivers/clk/meson/a1-pll.h | 6 +++
> > 2 files changed, 85 insertions(+)
> >
> > diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
> > index 60b2e53e7e51..af47ba308bbe 100644
> > --- a/drivers/clk/meson/a1-pll.c
> > +++ b/drivers/clk/meson/a1-pll.c
> > @@ -138,6 +138,82 @@ static struct clk_regmap hifi_pll = {
> > },
> > };
> >
> > +static const struct pll_mult_range sys_pll_mult_range = {
> > + .min = 32,
> > + .max = 64,
> > +};
> > +
> > +static const struct reg_sequence sys_pll_init_regs[] = {
> > + { .reg = ANACTRL_SYSPLL_CTRL1, .def = 0x01800000 },
> > + { .reg = ANACTRL_SYSPLL_CTRL2, .def = 0x00001100 },
> > + { .reg = ANACTRL_SYSPLL_CTRL3, .def = 0x10022300 },
> > + { .reg = ANACTRL_SYSPLL_CTRL4, .def = 0x00300000 },
> > + { .reg = ANACTRL_SYSPLL_CTRL0, .def = 0x01f18432 },
> > +};
> > +
> > +static struct clk_regmap sys_pll = {
> > + .data = &(struct meson_clk_pll_data){
> > + .en = {
> > + .reg_off = ANACTRL_SYSPLL_CTRL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .m = {
> > + .reg_off = ANACTRL_SYSPLL_CTRL0,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .n = {
> > + .reg_off = ANACTRL_SYSPLL_CTRL0,
> > + .shift = 10,
> > + .width = 5,
> > + },
> > + .frac = {
> > + .reg_off = ANACTRL_SYSPLL_CTRL1,
> > + .shift = 0,
> > + .width = 19,
> > + },
> > + .l = {
> > + .reg_off = ANACTRL_SYSPLL_STS,
> > + .shift = 31,
> > + .width = 1,
> > + },
> > + .current_en = {
> > + .reg_off = ANACTRL_SYSPLL_CTRL0,
> > + .shift = 26,
> > + .width = 1,
> > + },
> > + .l_detect = {
> > + .reg_off = ANACTRL_SYSPLL_CTRL2,
> > + .shift = 6,
> > + .width = 1,
> > + },
> > + .range = &sys_pll_mult_range,
> > + .init_regs = sys_pll_init_regs,
> > + .init_count = ARRAY_SIZE(sys_pll_init_regs),
>
> Like other 'fishy' flags, I would like a clear comment why this flag is
> required so, 2y from now, we will know why it was put there and how we
> can deal with it.
>
Yep, you are totally correct. The proper comment is required for that.
> > + .flags = CLK_MESON_PLL_INIT_ONCE,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sys_pll",
> > + .ops = &meson_clk_pll_ops,
> > + .parent_names = (const char *[]){ "syspll_in" },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor sys_pll_div16 = {
> > + .mult = 1,
> > + .div = 16,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sys_pll_div16",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &sys_pll.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
>
> Unlike the fdivs, this fixed divider is not part of the diagram
> describing the syspll clock.
>
> IMO, it could as well be in peripheral controller because it exists
> (from what I can see) just testing purposes, to make the sys pll
> observable through tst_out or gen_clk.
>
> It also looks less awkward in the bindings.
>
In any case, it is necessary to introduce a new connection. Instead of
using 'sys_pll_div16', it will now be called 'sys_pll'. I agree with you
that this change will make the code more elegant.
> > +
> > static struct clk_fixed_factor fclk_div2_div = {
> > .mult = 1,
> > .div = 2,
> > @@ -283,6 +359,8 @@ static struct clk_hw *a1_pll_hw_clks[] = {
> > [CLKID_FCLK_DIV5] = &fclk_div5.hw,
> > [CLKID_FCLK_DIV7] = &fclk_div7.hw,
> > [CLKID_HIFI_PLL] = &hifi_pll.hw,
> > + [CLKID_SYS_PLL] = &sys_pll.hw,
> > + [CLKID_SYS_PLL_DIV16] = &sys_pll_div16.hw,
> > };
> >
> > static struct clk_regmap *const a1_pll_regmaps[] = {
> > @@ -293,6 +371,7 @@ static struct clk_regmap *const a1_pll_regmaps[] = {
> > &fclk_div5,
> > &fclk_div7,
> > &hifi_pll,
> > + &sys_pll,
> > };
> >
> > static struct regmap_config a1_pll_regmap_cfg = {
> > diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h
> > index 4be17b2bf383..666d9b2137e9 100644
> > --- a/drivers/clk/meson/a1-pll.h
> > +++ b/drivers/clk/meson/a1-pll.h
> > @@ -18,6 +18,12 @@
> > #define ANACTRL_FIXPLL_CTRL0 0x0
> > #define ANACTRL_FIXPLL_CTRL1 0x4
> > #define ANACTRL_FIXPLL_STS 0x14
> > +#define ANACTRL_SYSPLL_CTRL0 0x80
> > +#define ANACTRL_SYSPLL_CTRL1 0x84
> > +#define ANACTRL_SYSPLL_CTRL2 0x88
> > +#define ANACTRL_SYSPLL_CTRL3 0x8c
> > +#define ANACTRL_SYSPLL_CTRL4 0x90
> > +#define ANACTRL_SYSPLL_STS 0x94
> > #define ANACTRL_HIFIPLL_CTRL0 0xc0
> > #define ANACTRL_HIFIPLL_CTRL1 0xc4
> > #define ANACTRL_HIFIPLL_CTRL2 0xc8
>
>
> --
> Jerome
--
Thank you,
Dmitry
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