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Message-Id: <cover.1715708679.git.tjeznach@rivosinc.com>
Date: Tue, 14 May 2024 11:16:12 -0700
From: Tomasz Jeznach <tjeznach@...osinc.com>
To: Joerg Roedel <joro@...tes.org>,
Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>,
Paul Walmsley <paul.walmsley@...ive.com>
Cc: Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Anup Patel <apatel@...tanamicro.com>,
Sunil V L <sunilvl@...tanamicro.com>,
Nick Kossifidis <mick@....forth.gr>,
Sebastien Boeuf <seb@...osinc.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
devicetree@...r.kernel.org,
iommu@...ts.linux.dev,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux@...osinc.com,
Tomasz Jeznach <tjeznach@...osinc.com>
Subject: [PATCH v5 0/7] Linux RISC-V IOMMU Support
This patch series introduces support for RISC-V IOMMU architected
hardware into the Linux kernel.
The RISC-V IOMMU specification, which this series is based on, is
ratified and available at GitHub/riscv-non-isa [1].
At a high level, the RISC-V IOMMU specification defines:
1) Data structures:
- Device-context: Associates devices with address spaces and holds
per-device parameters for address translations.
- Process-contexts: Associates different virtual address spaces based
on device-provided process identification numbers.
- MSI page table configuration used to direct an MSI to a guest
interrupt file in an IMSIC.
2) In-memory queue interface:
- Command-queue for issuing commands to the IOMMU.
- Fault/event queue for reporting faults and events.
- Page-request queue for reporting "Page Request" messages received
from PCIe devices.
- Message-signaled and wire-signaled interrupt mechanisms.
3) Memory-mapped programming interface:
- Mandatory and optional register layout and description.
- Software guidelines for device initialization and capabilities discovery.
This series introduces RISC-V IOMMU hardware initialization and complete
single-stage translation with paging domain support.
The patches are organized as follows:
Patch 1: Introduces minimal required device tree bindings for the driver.
Patch 2: Defines RISC-V IOMMU data structures, hardware programming interface
registers layout, and minimal initialization code for enabling global
pass-through for all connected masters.
Patch 3: Implements the device driver for PCIe implementation of RISC-V IOMMU
architected hardware.
Patch 4: Introduces IOMMU interfaces to the kernel subsystem.
Patch 5: Implements device directory management with discovery sequences for
I/O mapped or in-memory device directory table location, hardware
capabilities discovery, and device to domain attach implementation.
Patch 6: Implements command and fault queue, and introduces directory cache
invalidation sequences.
Patch 7: Implements paging domain, using highest page-table mode advertised
by the hardware. This series enables only 4K mappings; complete support
for large page mappings will be introduced in follow-up patch series.
Follow-up patch series, providing large page support and updated walk cache
management based on the revised specification, and complete ATS/PRI/SVA support,
will be posted to GitHub [2].
Changes from v4:
- riscv_iommu_iotlb_inval(): barriers, domain attach synchronization, comments
- riscv_iommu_bond_unlink(): invalidate IOATC on last unlink call
- riscv_iommu_cmd_sync(): separate IOFENCE.C call with optional timeout
- probe_device() fix: check dev_iommu_fwspec_get() return value
- editorial changes: s/IVEC/IVCEC, phys_to_ppn(va)
Patch series depends on (applied to iommu-next):
IOMMU memory observability, v6 [3]
iommu, dma-mapping: Simplify arch_setup_dma_ops(), v4 [4]
Best regards,
Tomasz Jeznach
[1] link: https://github.com/riscv-non-isa/riscv-iommu
[2] link: https://github.com/tjeznach/linux
[3] link: https://lore.kernel.org/linux-iommu/20240413002522.1101315-1-pasha.tatashin@soleen.com/
[4] link: https://lore.kernel.org/linux-iommu/cover.1713523152.git.robin.murphy@arm.com/
v4 link: https://lore.kernel.org/linux-iommu/cover.1714752293.git.tjeznach@rivosinc.com/
v3 link: https://lore.kernel.org/linux-iommu/cover.1714494653.git.tjeznach@rivosinc.com/
v2 link: https://lore.kernel.org/linux-iommu/cover.1713456597.git.tjeznach@rivosinc.com/
v1 link: https://lore.kernel.org/linux-iommu/cover.1689792825.git.tjeznach@rivosinc.com/
Tomasz Jeznach (7):
dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU
iommu/riscv: Add RISC-V IOMMU platform device driver
iommu/riscv: Add RISC-V IOMMU PCIe device driver
iommu/riscv: Enable IOMMU registration and device probe.
iommu/riscv: Device directory management.
iommu/riscv: Command and fault queue support
iommu/riscv: Paging domain support
.../bindings/iommu/riscv,iommu.yaml | 147 ++
MAINTAINERS | 8 +
drivers/iommu/Kconfig | 1 +
drivers/iommu/Makefile | 2 +-
drivers/iommu/riscv/Kconfig | 20 +
drivers/iommu/riscv/Makefile | 3 +
drivers/iommu/riscv/iommu-bits.h | 782 ++++++++
drivers/iommu/riscv/iommu-pci.c | 119 ++
drivers/iommu/riscv/iommu-platform.c | 92 +
drivers/iommu/riscv/iommu.c | 1674 +++++++++++++++++
drivers/iommu/riscv/iommu.h | 88 +
11 files changed, 2935 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
create mode 100644 drivers/iommu/riscv/Kconfig
create mode 100644 drivers/iommu/riscv/Makefile
create mode 100644 drivers/iommu/riscv/iommu-bits.h
create mode 100644 drivers/iommu/riscv/iommu-pci.c
create mode 100644 drivers/iommu/riscv/iommu-platform.c
create mode 100644 drivers/iommu/riscv/iommu.c
create mode 100644 drivers/iommu/riscv/iommu.h
base-commit: a38297e3fb012ddfa7ce0321a7e5a8daeb1872b6
message-id: 20240413002522.1101315-1-pasha.tatashin@...een.com
message-id: cover.1713523152.git.robin.murphy@....com
--
2.34.1
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