linux-kernel - Re: [PATCH] drm/stm: dsi: relax mode

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Date: Wed, 15 May 2024 09:42:34 +0200
From: Sean Nyekjaer <sean@...nix.com>
To: Yannick FERTRE <yannick.fertre@...s.st.com>
Cc: Raphael Gallais-Pou <raphael.gallais-pou@...s.st.com>, 
	Philippe Cornu <philippe.cornu@...s.st.com>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, 
	Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, 
	David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>, 
	Maxime Coquelin <mcoquelin.stm32@...il.com>, Alexandre Torgue <alexandre.torgue@...s.st.com>, 
	Robert Foss <rfoss@...nel.org>, Antonio Borneo <antonio.borneo@...s.st.com>, 
	dri-devel@...ts.freedesktop.org, linux-stm32@...md-mailman.stormreply.com, 
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] drm/stm: dsi: relax mode_valid clock tolerance

On Wed, May 15, 2024 at 08:39:49AM UTC, Yannick FERTRE wrote:
> Hi Sean,
> 
> thanks for your patch.
> 
> Tested-by: Yannick Fertre <yannick.fertre@...s.st.com>
> 
> I think that a helper could be useful in simplifying this part.
> This might be reworked when a new helper will be implemented.
> 
> Best regards

Hi Yannick,

Will this mean that this will patch will go in?

I still have plans to do the helper, but I'm limited on time :)

/Sean

> 
> 
> On 4/22/24 16:05, Sean Nyekjaer wrote:
> > On Fri, Mar 22, 2024 at 11:47:31AM +0100, Sean Nyekjaer wrote:
> > > When using the DSI interface via DSI2LVDS bridge, it seems a bit harsh
> > > to reguire the requested and the actual px clock to be within
> > > 50Hz. A typical LVDS display requires the px clock to be within +-10%.
> > > 
> > > In case for HDMI .5% tolerance is required.
> > > 
> > > Fixes: e01356d18273 ("drm/stm: dsi: provide the implementation of mode_valid()")
> > > Signed-off-by: Sean Nyekjaer <sean@...nix.com>
> > > ---
> > Any feedback on this?
> > 
> > >   drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 7 +++----
> > >   1 file changed, 3 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> > > index d5f8c923d7bc..97936b0ef702 100644
> > > --- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> > > +++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> > > @@ -322,8 +322,6 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> > >   	return 0;
> > >   }
> > > -#define CLK_TOLERANCE_HZ 50
> > > -
> > >   static enum drm_mode_status
> > >   dw_mipi_dsi_stm_mode_valid(void *priv_data,
> > >   			   const struct drm_display_mode *mode,
> > > @@ -375,9 +373,10 @@ dw_mipi_dsi_stm_mode_valid(void *priv_data,
> > >   		/*
> > >   		 * Filter modes according to the clock value, particularly useful for
> > >   		 * hdmi modes that require precise pixel clocks.
> > > +		 * Check that px_clock is within .5% tolerance.
> > >   		 */
> > > -		if (px_clock_hz < target_px_clock_hz - CLK_TOLERANCE_HZ ||
> > > -		    px_clock_hz > target_px_clock_hz + CLK_TOLERANCE_HZ)
> > > +		if (px_clock_hz < mult_frac(target_px_clock_hz, 995, 1000) ||
> > > +		    px_clock_hz > mult_frac(target_px_clock_hz, 1005, 1000))
> > >   			return MODE_CLOCK_RANGE;
> > >   		/* sync packets are codes as DSI short packets (4 bytes) */
> > > -- 
> > > 2.44.0
> > >