linux-kernel - Re: [PATCH 3/3] pinctrl: rockchip: add rk3308b SoC support

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Message-ID: <d2c0bc2b-91a1-4533-bd14-3973277b5f6f@wanadoo.fr>
Date: Wed, 15 May 2024 19:00:38 +0200
From: Christophe JAILLET <christophe.jaillet@...adoo.fr>
To: Dmitry Yashin <dmt.yashin@...il.com>,
 Linus Walleij <linus.walleij@...aro.org>, Heiko Stuebner <heiko@...ech.de>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Rob Herring <robh@...nel.org>
Cc: Luca Ceresoli <luca.ceresoli@...tlin.com>,
 Jianqun Xu <jay.xu@...k-chips.com>, devicetree@...r.kernel.org,
 linux-gpio@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/3] pinctrl: rockchip: add rk3308b SoC support

Le 15/05/2024 à 14:16, Dmitry Yashin a écrit :
> Add pinctrl support for rk3308b. This pin controller much the same as
> rk3308's, but with additional iomux routes and 3bit iomuxes selected
> via gpio##_sel_src_ctrl registers. Set them up in the function
> rk3308b_soc_sel_src_init to use new 3bit iomuxes over some 2bit old ones.
> 
> Fixes: 1f3e25a06883 ("pinctrl: rockchip: fix RK3308 pinmux bits")
> Signed-off-by: Dmitry Yashin <dmt.yashin@...il.com>
> ---
>   drivers/pinctrl/pinctrl-rockchip.c | 200 +++++++++++++++++++++++++++++
>   drivers/pinctrl/pinctrl-rockchip.h |   1 +
>   2 files changed, 201 insertions(+)

Hi,

> 
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index cc647db76927..15d2045f929e 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -632,6 +632,115 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
>   	},
>   };
>   
> +static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = {

It is likely that it would require some other changes, but it looks to 
be a good candidate for static const struct.

> +	{
> +		/* gpio1b6_sel */
> +		.num = 1,
> +		.pin = 14,
> +		.reg = 0x28,
> +		.bit = 12,
> +		.mask = 0xf
> +	}, {

..

> @@ -882,6 +991,35 @@ static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
>   	RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
>   };
>   
> +static struct rockchip_mux_route_data rk3308b_mux_route_data[] = {

Same

> +	RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
> +	RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
> +	RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
> +	RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */

..

> @@ -3746,6 +3929,21 @@ static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
>   		.schmitt_calc_reg	= rk3308_calc_schmitt_reg_and_bit,
>   };
>   
> +static struct rockchip_pin_ctrl rk3308b_pin_ctrl = {

This one could be constify without any other changes I think (and also 
makes more sense because of its function pointers)

Just my 2c.

CJ

> +		.pin_banks		= rk3308_pin_banks,
> +		.nr_banks		= ARRAY_SIZE(rk3308_pin_banks),
> +		.label			= "RK3308b-GPIO",
> +		.type			= RK3308B,
> +		.grf_mux_offset		= 0x0,
> +		.iomux_recalced		= rk3308b_mux_recalced_data,
> +		.niomux_recalced	= ARRAY_SIZE(rk3308b_mux_recalced_data),
> +		.iomux_routes		= rk3308b_mux_route_data,
> +		.niomux_routes		= ARRAY_SIZE(rk3308b_mux_route_data),
> +		.pull_calc_reg		= rk3308_calc_pull_reg_and_bit,
> +		.drv_calc_reg		= rk3308_calc_drv_reg_and_bit,
> +		.schmitt_calc_reg	= rk3308_calc_schmitt_reg_and_bit,
> +};

..