| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20240516032436.2681828-1-quic_devipriy@quicinc.com>
Date: Thu, 16 May 2024 08:54:32 +0530
From: devi priya <quic_devipriy@...cinc.com>
To: vkoul@...nel.org, kishon@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, dmitry.baryshkov@...aro.org,
neil.armstrong@...aro.org, quic_msarkar@...cinc.com,
quic_qianyu@...cinc.com, abel.vesa@...aro.org, quic_cang@...cinc.com,
linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: quic_devipriy@...cinc.com
Subject: [PATCH V4 0/4] Add support for PCIe PHY in IPQ9574
This series adds support for a single-lane and two-lane PCIe PHYs
found on Qualcomm IPQ9574 platform.
[V4]
Picked up the R-b/A-b tags.
Split the phy driver and headers to individual patches.
[V3]
https://lore.kernel.org/linux-arm-msm/20240512082541.1805335-1-quic_devipriy@quicinc.com/
[V2]
https://lore.kernel.org/linux-arm-msm/20230519085723.15601-1-quic_devipriy@quicinc.com/
[V1]
https://lore.kernel.org/linux-arm-msm/20230421124150.21190-1-quic_devipriy@quicinc.com/
devi priya (4):
dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ9574 QMP PCIe
PHYs
phy: qcom-qmp: Add missing offsets for Qserdes PLL registers.
phy: qcom-qmp: Add missing register definitions for PCS V5
phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 PCIEs
.../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 309 ++++++++++++++++++
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 +
.../phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 3 +
4 files changed, 328 insertions(+)
--
2.34.1
Powered by blists - more mailing lists