linux-kernel - [PATCH 1/2] dt-bindings: dma: Add reg-names to nvidia,tegra210-adma

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20240520122351.1691058-2-spujar@nvidia.com>
Date: Mon, 20 May 2024 12:23:50 +0000
From: Sameer Pujar <spujar@...dia.com>
To: <vkoul@...nel.org>, <thierry.reding@...il.com>,
	<dmaengine@...r.kernel.org>
CC: <jonathanh@...dia.com>, <linux-tegra@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <mkumard@...dia.com>, <spujar@...dia.com>,
	<ldewangan@...dia.com>
Subject: [PATCH 1/2] dt-bindings: dma: Add reg-names to nvidia,tegra210-adma

From: Mohan Kumar <mkumard@...dia.com>

For Non-Hypervisor mode, Tegra ADMA driver requires the register
resource range to include both global and channel page in the reg
entry. For Hypervisor more, Tegra ADMA driver requires only the
channel page and global page range is not allowed for access.

Add reg-names DT binding for Hypervisor mode to help driver to
differentiate the config between Hypervisor and Non-Hypervisor
mode of execution.

Signed-off-by: Mohan Kumar <mkumard@...dia.com>
Signed-off-by: Sameer Pujar <spujar@...dia.com>
---
 .../devicetree/bindings/dma/nvidia,tegra210-adma.yaml  | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml
index 877147e95ecc..ede47f4a3eec 100644
--- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml
@@ -29,8 +29,18 @@ properties:
           - const: nvidia,tegra186-adma
 
   reg:
+    description: |
+      For hypervisor mode, the address range should include a
+      ADMA channel page address range, for non-hypervisor mode
+      it starts with ADMA base address covering Global and Channel
+      page address range.
     maxItems: 1
 
+  reg-names:
+    description: only required for Hypervisor mode.
+    items:
+      - const: vm
+
   interrupts:
     description: |
       Should contain all of the per-channel DMA interrupts in
-- 
2.45.1