linux-kernel - Re: [PATCH v2 1/2] ASoC: dt-bindings: fsl,xcvr: Add compatible string for i.MX95

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Tue, 21 May 2024 11:44:53 +0800
From: Shengjiu Wang <shengjiu.wang@...il.com>
To: Rob Herring <robh@...nel.org>
Cc: Shengjiu Wang <shengjiu.wang@....com>, lgirdwood@...il.com, broonie@...nel.org, 
	krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org, 
	linux-sound@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Xiubo.Lee@...il.com, festevam@...il.com, 
	nicoleotsuka@...il.com, perex@...ex.cz, tiwai@...e.com, 
	alsa-devel@...a-project.org, linuxppc-dev@...ts.ozlabs.org
Subject: Re: [PATCH v2 1/2] ASoC: dt-bindings: fsl,xcvr: Add compatible string
 for i.MX95

On Tue, May 21, 2024 at 12:16 AM Rob Herring <robh@...nel.org> wrote:
>
> On Tue, May 14, 2024 at 11:12:08AM +0800, Shengjiu Wang wrote:
> > Add compatible string "fsl,imx95-xcvr" for i.MX95 platform.
> >
> > The difference between each platform is in below table.
> >
> > +---------+--------+----------+--------+
> > |  SOC          |  PHY   | eARC/ARC | SPDIF  |
> > +---------+--------+----------+--------+
> > | i.MX8MP |  V1    |  Yes     |  Yes   |
> > +---------+--------+----------+--------+
> > | i.MX93  |  N/A   |  N/A     |  Yes   |
> > +---------+--------+----------+--------+
> > | i.MX95  |  V2    |  N/A     |  Yes   |
> > +---------+--------+----------+--------+
> >
> > On i.MX95, there are two PLL clock sources, they are the parent
> > clocks of the XCVR root clock. one is for 8kHz series rates, named
> > as 'pll8k', another one is for 11kHz series rates, named as 'pll11k'.
> > They are optional clocks, if there are such clocks, then the driver
> > can switch between them to support more accurate sample rates.
> >
> > As 'pll8k' and 'pll11k' are optional, then add 'minItems: 4'
> > for clocks and clock-names properties.
> >
> > Signed-off-by: Shengjiu Wang <shengjiu.wang@....com>
> > ---
> >  .../devicetree/bindings/sound/fsl,xcvr.yaml   | 55 +++++++++++++++----
> >  1 file changed, 45 insertions(+), 10 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml b/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml
> > index 0eb0c1ba8710..70bcde33e986 100644
> > --- a/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml
> > +++ b/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml
> > @@ -22,6 +22,7 @@ properties:
> >      enum:
> >        - fsl,imx8mp-xcvr
> >        - fsl,imx93-xcvr
> > +      - fsl,imx95-xcvr
> >
> >    reg:
> >      items:
> > @@ -44,18 +45,12 @@ properties:
> >      minItems: 1
> >
> >    clocks:
> > -    items:
> > -      - description: Peripheral clock
> > -      - description: PHY clock
> > -      - description: SPBA clock
> > -      - description: PLL clock
>
> Leave these here and add pll8k and pll11k.
>
> > +    minItems: 4
>
> Keep this.
>
> > +    maxItems: 6
> >
> >    clock-names:
> > -    items:
> > -      - const: ipg
> > -      - const: phy
> > -      - const: spba
> > -      - const: pll_ipg
> > +    minItems: 4
> > +    maxItems: 6
>
> Same here.
>
> >
> >    dmas:
> >      items:
> > @@ -97,6 +92,46 @@ allOf:
> >        properties:
> >          interrupts:
> >            maxItems: 1
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - fsl,imx95-xcvr
> > +    then:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: Peripheral clock
> > +            - description: PHY clock
> > +            - description: SPBA clock
> > +            - description: PLL clock
> > +            - description: PLL clock source for 8kHz series
> > +            - description: PLL clock source for 11kHz series
> > +          minItems: 4
> > +        clock-names:
> > +          items:
> > +            - const: ipg
> > +            - const: phy
> > +            - const: spba
> > +            - const: pll_ipg
> > +            - const: pll8k
> > +            - const: pll11k
> > +          minItems: 4
>
> Drop all this.
>
> > +    else:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: Peripheral clock
> > +            - description: PHY clock
> > +            - description: SPBA clock
> > +            - description: PLL clock
> > +        clock-names:
> > +          items:
> > +            - const: ipg
> > +            - const: phy
> > +            - const: spba
> > +            - const: pll_ipg
>
> And for this case, you just need 'maxItems: 4'.
>

Thanks for the comments.

I will address them in the next version.

Best regards
Shengjiu Wang