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Date: Tue, 21 May 2024 09:36:19 +0000
From: SkyLake Huang (黃啟澤)
	<SkyLake.Huang@...iatek.com>
To: "linux@...linux.org.uk" <linux@...linux.org.uk>, "andrew@...n.ch"
	<andrew@...n.ch>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
	"kuba@...nel.org" <kuba@...nel.org>, "pabeni@...hat.com" <pabeni@...hat.com>,
	"edumazet@...gle.com" <edumazet@...gle.com>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "dqfext@...il.com"
	<dqfext@...il.com>, Steven Liu (劉人豪)
	<steven.liu@...iatek.com>, "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"matthias.bgg@...il.com" <matthias.bgg@...il.com>, "davem@...emloft.net"
	<davem@...emloft.net>, "hkallweit1@...il.com" <hkallweit1@...il.com>,
	"angelogioacchino.delregno@...labora.com"
	<angelogioacchino.delregno@...labora.com>, "daniel@...rotopia.org"
	<daniel@...rotopia.org>
Subject: Re: [PATCH net-next v2 5/5] net: phy: add driver for built-in 2.5G
 ethernet PHY on MT7988

On Mon, 2024-05-20 at 18:48 +0100, Russell King (Oracle) wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On Mon, May 20, 2024 at 03:02:21PM +0200, Andrew Lunn wrote:
> > > Actually this phy is strictly binded to (XFI)MAC on this
> platform.
> > > So I directly disable HDX feature of PHY.
> > 
> > Sorry, i don't follow your answer:
> > 
> > Can the PHY do half duplex?
> > Can the MAC do half duplex?

Sorry about ambiguity.
- Can the PHY do half duplex?
The short answer is no. I clarify the comments like below so everyone
should know this phy's capability

/* This phy can't handle collision, and neither can (XFI)MAC it's
connected to.
 * Although it can do HDX handshake, it doesn't support CSMA/CD that
HDX requires.
 */
linkmode_clear_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev-
>supported);

- Can the MAC do half duplex?
No.
Daniel has explained MT7988 SoC's network interfaces in v1 patch:
https://lore.kernel.org/netdev/Zjumd3bnZDu9LYGH@makrotopia.org/

- GMAC0 is typically connected as conduit to a 4-port MT7530-like DSA
  switch offering 4 1GE user ports. PHY driver mediatek-ge-soc.c takes
  care of those, and yes, they do need some "care"...

- GMAC1 can be used with the internal 2.5GE PHY (ie. with the driver
  discussed here) OR for to connect an external PHY or SFP via
  1000Base-X, 2500Base-X, SGMII, 5GBase-R, 10GBase-R or USXGMII.

- GMAC2 is can only be used with an external PHY or SFP using
  1000Base-X, 2500Base-X, SGMII, 5GBase-R, 10GBa

Actually, internal 2.5GbE PHY is connected to XFIMAC via XMGII.
According to IEEE std 802.3-2018 section 46.1(page.188). XGMII provides
for full duplex operation only.

> > 
> > The part which cannot do half-duplex should be the part which
> disables
> > half-duplex.
> 
> Note that if the PHY is doing rate adaption (preferably in a form
> that
> it can control the MAC transmission rate), then even if the MAC can't
> do half-duplex, the PHY can still do half-duplex.
> 
> -- 
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Yes, this phy is doing rate adaption. But just like what I said above,
its rate adaption module can't support CSMA/CD.

Sky

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