linux-kernel - RE: [PATCH 4/5] vfio/type1: Flush CPU caches on DMA pages in non-coherent domains

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <BN9PR11MB527604CDF2E7FA49176200028CEB2@BN9PR11MB5276.namprd11.prod.outlook.com>
Date: Wed, 22 May 2024 23:26:21 +0000
From: "Tian, Kevin" <kevin.tian@...el.com>
To: Jason Gunthorpe <jgg@...dia.com>
CC: Alex Williamson <alex.williamson@...hat.com>, "Vetter, Daniel"
	<daniel.vetter@...el.com>, "Zhao, Yan Y" <yan.y.zhao@...el.com>,
	"kvm@...r.kernel.org" <kvm@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "x86@...nel.org" <x86@...nel.org>,
	"iommu@...ts.linux.dev" <iommu@...ts.linux.dev>, "pbonzini@...hat.com"
	<pbonzini@...hat.com>, "seanjc@...gle.com" <seanjc@...gle.com>,
	"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
	"luto@...nel.org" <luto@...nel.org>, "peterz@...radead.org"
	<peterz@...radead.org>, "tglx@...utronix.de" <tglx@...utronix.de>,
	"mingo@...hat.com" <mingo@...hat.com>, "bp@...en8.de" <bp@...en8.de>,
	"hpa@...or.com" <hpa@...or.com>, "corbet@....net" <corbet@....net>,
	"joro@...tes.org" <joro@...tes.org>, "will@...nel.org" <will@...nel.org>,
	"robin.murphy@....com" <robin.murphy@....com>, "baolu.lu@...ux.intel.com"
	<baolu.lu@...ux.intel.com>, "Liu, Yi L" <yi.l.liu@...el.com>
Subject: RE: [PATCH 4/5] vfio/type1: Flush CPU caches on DMA pages in
 non-coherent domains

> From: Jason Gunthorpe <jgg@...dia.com>
> Sent: Wednesday, May 22, 2024 8:30 PM
> 
> On Wed, May 22, 2024 at 06:24:14AM +0000, Tian, Kevin wrote:
> > I'm fine to do a special check in the attach path to enable the flush
> > only for Intel GPU.
> 
> We already effectively do this already by checking the domain
> capabilities. Only the Intel GPU will have a non-coherent domain.
> 

I'm confused. In earlier discussions you wanted to find a way to not
publish others due to the check of non-coherent domain, e.g. some
ARM SMMU cannot force snoop.

Then you and Alex discussed the possibility of reducing pessimistic
flushes by virtualizing the PCI NOSNOOP bit.

With that in mind I was thinking whether we explicitly enable this
flush only for Intel GPU instead of checking non-coherent domain
in the attach path, since it's the only device with such requirement.

Did I misunderstand the concern here?