linux-kernel - Re: [PATCH v4 0/2] riscv: Extension parsing fixes

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Message-Id: 
 <171642190760.9409.9505694012625639228.git-patchwork-notify@kernel.org>
Date: Wed, 22 May 2024 23:51:47 +0000
From: patchwork-bot+linux-riscv@...nel.org
To: Charlie Jenkins <charlie@...osinc.com>
Cc: linux-riscv@...ts.infradead.org, paul.walmsley@...ive.com,
 palmer@...belt.com, aou@...s.berkeley.edu, guoren@...nel.org,
 conor@...nel.org, conor.dooley@...rochip.com, cleger@...osinc.com,
 evan@...osinc.com, palmer@...osinc.com, linux-kernel@...r.kernel.org,
 alexghiti@...osinc.com, ajones@...tanamicro.com
Subject: Re: [PATCH v4 0/2] riscv: Extension parsing fixes

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@...osinc.com>:

On Thu, 02 May 2024 21:50:49 -0700 you wrote:
> This series contains two minor fixes for the extension parsing in
> cpufeature.c.
> 
> Some T-Head boards without vector 1.0 support report "v" in the isa
> string in their DT which will cause the kernel to run vector code. The
> code to blacklist "v" from these boards was doing so by using
> riscv_cached_mvendorid() which has not been populated at the time of
> extension parsing. This fix instead greedily reads the mvendorid CSR of
> the boot hart to determine if the cpu is from T-Head.
> 
> [...]

Here is the summary with links:
  - [v4,1/2] riscv: cpufeature: Fix thead vector hwcap removal
    https://git.kernel.org/riscv/c/e482eab4d1eb
  - [v4,2/2] riscv: cpufeature: Fix extension subset checking
    https://git.kernel.org/riscv/c/e67e98ee8952

You are awesome, thank you!
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