linux-kernel - Re: [PATCH v2] KVM: SEV-ES: Don't intercept MSR_IA32

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Message-ID: <9316ce80-b9c5-44ce-ab66-e7cdb6893c1f@amd.com>
Date: Wed, 22 May 2024 11:41:10 +0530
From: Ravi Bangoria <ravi.bangoria@....com>
To: Sean Christopherson <seanjc@...gle.com>
Cc: pbonzini@...hat.com, thomas.lendacky@....com, tglx@...utronix.de,
 mingo@...hat.com, bp@...en8.de, dave.hansen@...ux.intel.com, x86@...nel.org,
 hpa@...or.com, michael.roth@....com, nikunj.dadhania@....com,
 kvm@...r.kernel.org, linux-kernel@...r.kernel.org, santosh.shukla@....com,
 ravi.bangoria@....com
Subject: Re: [PATCH v2] KVM: SEV-ES: Don't intercept MSR_IA32_DEBUGCTLMSR for
 SEV-ES guests

On 5/22/2024 2:01 AM, Sean Christopherson wrote:
> On Mon, May 20, 2024, Ravi Bangoria wrote:
>> On 17-May-24 8:01 PM, Sean Christopherson wrote:
>>> On Fri, May 17, 2024, Ravi Bangoria wrote:
>>>> On 08-May-24 12:37 AM, Sean Christopherson wrote:
>>>>> So unless I'm missing something, the only reason to ever disable LBRV would be
>>>>> for performance reasons.  Indeed the original commits more or less says as much:
>>>>>
>>>>>   commit 24e09cbf480a72f9c952af4ca77b159503dca44b
>>>>>   Author:     Joerg Roedel <joerg.roedel@....com>
>>>>>   AuthorDate: Wed Feb 13 18:58:47 2008 +0100
>>>>>
>>>>>     KVM: SVM: enable LBR virtualization
>>>>>     
>>>>>     This patch implements the Last Branch Record Virtualization (LBRV) feature of
>>>>>     the AMD Barcelona and Phenom processors into the kvm-amd module. It will only
>>>>>     be enabled if the guest enables last branch recording in the DEBUG_CTL MSR. So
>>>>>     there is no increased world switch overhead when the guest doesn't use these
>>>>>     MSRs.
>>>>>
>>>>> but what it _doesn't_ say is what the world switch overhead is when LBRV is
>>>>> enabled.  If the overhead is small, e.g. 20 cycles?, then I see no reason to
>>>>> keep the dynamically toggling.
>>>>>
>>>>> And if we ditch the dynamic toggling, then this patch is unnecessary to fix the
>>>>> LBRV issue.  It _is_ necessary to actually let the guest use the LBRs, but that's
>>>>> a wildly different changelog and justification.
>>>>
>>>> The overhead might be less for legacy LBR. But upcoming hw also supports
>>>> LBR Stack Virtualization[1]. LBR Stack has total 34 MSRs (two control and
>>>> 16*2 stack). Also, Legacy and Stack LBR virtualization both are controlled
>>>> through the same VMCB bit. So I think I still need to keep the dynamic
>>>> toggling for LBR Stack virtualization.
>>>
>>> Please get performance number so that we can make an informed decision.  I don't
>>> want to carry complexity because we _think_ the overhead would be too high.
>>
>> LBR Virtualization overhead for guest entry + exit roundtrip is ~450 cycles* on
> 
> Ouch.  Just to clearify, that's for LBR Stack Virtualization, correct?

Includes both, since there is a single enable bit shared by them.

> Ugh, I was going to say that we could always enable "legacy" LBR virtualization,
> and do the dynamic toggling iff DebugExtnCtl.LBRS=1, but they share an enabling
> flag.  What a mess.

Agreed. can't help :(

>> a Genoa machine. Also, LBR MSRs (except MSR_AMD_DBG_EXTN_CFG) are of swap type
>> C so this overhead is only for guest MSR save/restore.
> 
> Lovely.
> 
> Have I mentioned that the SEV-ES behavior of force-enabling every feature under
> the sun is really, really annoying?
> 
> Anyways, I agree that we need to keep the dynamic toggling.

Sure. Will prepare v3 accordingly.

Thanks,
Ravi