lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <e856dbde-c712-473f-a761-cd29d6e8d8b5@collabora.com>
Date: Wed, 22 May 2024 09:17:42 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Sergio Paracuellos <sergio.paracuellos@...il.com>,
 devicetree@...r.kernel.org
Cc: linux-pci@...r.kernel.org, krzk+dt@...nel.org, robh@...nel.org,
 kw@...ux.com, lpieralisi@...nel.org, bhelgaas@...gle.com,
 conor+dt@...nel.org, linux-kernel@...r.kernel.org,
 Krzysztof Kozlowski <krzk@...nel.org>
Subject: Re: [PATCH] dt-bindings: PCI: mediatek,mt7621-pcie: add PCIe host
 topology ascii graph

Il 22/05/24 06:43, Sergio Paracuellos ha scritto:
> MediaTek MT7621 PCIe subsys supports a single Root Complex (RC) with 3 Root
> Ports. Add PCIe host topology ascii graph to the binding for completeness.
> 
> Suggested-by: Krzysztof Kozlowski <krzk@...nel.org>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@...il.com>

Lovely.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>

> ---
>   .../bindings/pci/mediatek,mt7621-pcie.yaml    | 29 +++++++++++++++++++
>   1 file changed, 29 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml
> index 6fba42156db6..c41608863d6c 100644
> --- a/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml
> @@ -13,6 +13,35 @@ description: |+
>     MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
>     with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
>   
> +                          MT7621 PCIe HOST Topology
> +
> +                                   .-------.
> +                                   |       |
> +                                   |  CPU  |
> +                                   |       |
> +                                   '-------'
> +                                       |
> +                                       |
> +                                       |
> +                                       v
> +                              .------------------.
> +                  .-----------|  HOST/PCI Bridge |------------.
> +                  |           '------------------'            | Type1
> +             BUS0 |                     |                     | Access
> +                  v                     v                     v On Bus0
> +          .-------------.        .-------------.       .-------------.
> +          | VIRTUAL P2P |        | VIRTUAL P2P |       | VIRTUAL P2P |
> +          |    BUS0     |        |    BUS0     |       |    BUS0     |
> +          |    DEV0     |        |    DEV1     |       |    DEV2     |
> +          '-------------'        '-------------'       '-------------'
> +    Type0        |          Type0       |         Type0       |
> +   Access   BUS1 |         Access   BUS2|        Access   BUS3|
> +   On Bus1       v         On Bus2      v        On Bus3      v
> +           .----------.           .----------.          .----------.
> +           | Device 0 |           | Device 0 |          | Device 0 |
> +           |  Func 0  |           |  Func 0  |          |  Func 0  |
> +           '----------'           '----------'          '----------'
> +
>   allOf:
>     - $ref: /schemas/pci/pci-host-bridge.yaml#
>   


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ