linux-kernel - Re: [EXTERNAL] [PATCH 3/7] drm/bridge: cdns-dsi: Wait for Clk and Data Lanes to be ready

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Wed, 22 May 2024 10:23:37 +0000
From: Dominik Haller <D.Haller@...tec.de>
To: "Laurent.pinchart@...asonboard.com" <Laurent.pinchart@...asonboard.com>,
	"andrzej.hajda@...el.com" <andrzej.hajda@...el.com>,
	"neil.armstrong@...aro.org" <neil.armstrong@...aro.org>,
	"tzimmermann@...e.de" <tzimmermann@...e.de>,
	"tomi.valkeinen@...asonboard.com" <tomi.valkeinen@...asonboard.com>,
	"jyri.sarha@....fi" <jyri.sarha@....fi>, "rfoss@...nel.org"
	<rfoss@...nel.org>, "airlied@...il.com" <airlied@...il.com>,
	"a-bhatia1@...com" <a-bhatia1@...com>, "jonas@...boo.se" <jonas@...boo.se>,
	"jernej.skrabec@...il.com" <jernej.skrabec@...il.com>, "mripard@...nel.org"
	<mripard@...nel.org>, "maarten.lankhorst@...ux.intel.com"
	<maarten.lankhorst@...ux.intel.com>, "daniel@...ll.ch" <daniel@...ll.ch>
CC: "devarsht@...com" <devarsht@...com>, "u-kumar1@...com" <u-kumar1@...com>,
	"sam@...nborg.org" <sam@...nborg.org>, "j-choudhary@...com"
	<j-choudhary@...com>, "dri-devel@...ts.freedesktop.org"
	<dri-devel@...ts.freedesktop.org>, "j-luthra@...com" <j-luthra@...com>,
	"boris.brezillon@...tlin.com" <boris.brezillon@...tlin.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "nm@...com"
	<nm@...com>, "vigneshr@...com" <vigneshr@...com>,
	"kieran.bingham+renesas@...asonboard.com"
	<kieran.bingham+renesas@...asonboard.com>, "treding@...dia.com"
	<treding@...dia.com>, "praneeth@...com" <praneeth@...com>
Subject: Re: [EXTERNAL] [PATCH 3/7] drm/bridge: cdns-dsi: Wait for Clk and
 Data Lanes to be ready

Hi Aradhya,

this fixes the color-shift bug on our setup:
j721s2 -> ti,sn65dsi83 -> edt,etml1010g3dra



Tested-by: Dominik Haller <d.haller@...tec.de>


On Sat, 2024-05-11 at 21:00 +0530, Aradhya Bhatia wrote:
> Once the DSI Link and DSI Phy are initialized, the code needs to wait
> for Clk and Data Lanes to be ready, before continuing configuration.
> This is in accordance with the DSI Start-up procedure, found in the
> Technical Reference Manual of Texas Instrument's J721E SoC[0] which
> houses this DSI TX controller.
> 
> If the previous bridge (or crtc/encoder) are configured pre-maturely,
> the input signal FIFO gets corrupt. This introduces a color-shift on
> the
> display.
> 
> Allow the driver to wait for the clk and data lanes to get ready
> during
> DSI enable.
> 
> Fixes: e19233955d9e ("drm/bridge: Add Cadence DSI driver")
> Signed-off-by: Aradhya Bhatia <a-bhatia1@...com>
> ---
>  drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> index 557b037bbc67..05d2f4cc50da 100644
> --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> @@ -761,7 +761,7 @@ static void cdns_dsi_bridge_enable(struct
> drm_bridge *bridge)
>  	struct phy_configure_opts_mipi_dphy *phy_cfg = &output-
> >phy_opts.mipi_dphy;
>  	unsigned long tx_byte_period;
>  	struct cdns_dsi_cfg dsi_cfg;
> -	u32 tmp, reg_wakeup, div;
> +	u32 tmp, reg_wakeup, div, status;
>  	int nlanes;
>  
>  	if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
> @@ -778,6 +778,17 @@ static void cdns_dsi_bridge_enable(struct
> drm_bridge *bridge)
>  	cdns_dsi_init_link(dsi);
>  	cdns_dsi_hs_init(dsi);
>  
> +	/*
> +	 * Now that the DSI Link and DSI Phy are initialized,
> +	 * wait for the CLK and Data Lanes to be ready.
> +	 */
> +	tmp = CLK_LANE_RDY;
> +	for (int i = 0; i < nlanes; i++)
> +		tmp |= DATA_LANE_RDY(i);
> +
> +	WARN_ON_ONCE(readl_poll_timeout(dsi->regs + MCTL_MAIN_STS,
> status,
> +					status & tmp, 100, 0));
> +
>  	writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa),
>  	       dsi->regs + VID_HSIZE1);
>  	writel(HFP_LEN(dsi_cfg.hfp) | HACT_LEN(dsi_cfg.hact),