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Message-Id: <20240523094325.3514-1-dqfext@gmail.com>
Date: Thu, 23 May 2024 17:43:25 +0800
From: Qingfang Deng <dqfext@...il.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Cc: Xiao Wang <xiao.w.wang@...el.com>,
Qingfang Deng <qingfang.deng@...lower.com.cn>
Subject: [PATCH] riscv: hweight: relax assembly constraints
From: Qingfang Deng <qingfang.deng@...lower.com.cn>
rd and rs don't have to be the same.
Signed-off-by: Qingfang Deng <qingfang.deng@...lower.com.cn>
---
arch/riscv/include/asm/arch_hweight.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/include/asm/arch_hweight.h b/arch/riscv/include/asm/arch_hweight.h
index 85b2c443823e..613769b9cdc9 100644
--- a/arch/riscv/include/asm/arch_hweight.h
+++ b/arch/riscv/include/asm/arch_hweight.h
@@ -26,9 +26,9 @@ static __always_inline unsigned int __arch_hweight32(unsigned int w)
asm (".option push\n"
".option arch,+zbb\n"
- CPOPW "%0, %0\n"
+ CPOPW "%0, %1\n"
".option pop\n"
- : "+r" (w) : :);
+ : "=r" (w) : "r" (w) :);
return w;
@@ -57,9 +57,9 @@ static __always_inline unsigned long __arch_hweight64(__u64 w)
asm (".option push\n"
".option arch,+zbb\n"
- "cpop %0, %0\n"
+ "cpop %0, %1\n"
".option pop\n"
- : "+r" (w) : :);
+ : "=r" (w) : "r" (w) :);
return w;
--
2.34.1
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