linux-kernel - [RESEND v3 2/2] dt-bindings: riscv: cpus: add ref to interrupt-controller

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Message-Id: <20240523154748.22670-3-kanakshilledar111@protonmail.com>
Date: Thu, 23 May 2024 21:17:50 +0530
From: Kanak Shilledar <kanakshilledar@...il.com>
To: 
Cc: Kanak Shilledar <kanakshilledar111@...tonmail.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Samuel Holland <samuel.holland@...ive.com>,
	linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	Conor Dooley <conor.dooley@...rochip.com>
Subject: [RESEND v3 2/2] dt-bindings: riscv: cpus: add ref to interrupt-controller

removed the redundant properties for interrupt-controller
and provide reference to the riscv,cpu-intc.yaml which defines
the interrupt-controller. making the properties for riscv
interrupt-controller at a central place.

Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: Kanak Shilledar <kanakshilledar111@...tonmail.com>
---
Changes in v3:
- No change.
- Rolling out as RESEND.
Changes in v2:
- Fix warning of `type` is a required property during `make
dt_bindings_check`.
---
 .../interrupt-controller/riscv,cpu-intc.yaml  |  2 +-
 .../devicetree/bindings/riscv/cpus.yaml       | 21 +------------------
 2 files changed, 2 insertions(+), 21 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml
index c9c79e0870ff..6c229f3c6735 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml
@@ -61,7 +61,7 @@ required:
   - compatible
   - '#interrupt-cells'
   - interrupt-controller
-  
+
 additionalProperties: false
 
 examples:
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d87dd50f1a4b..f1241e5e8753 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -102,26 +102,7 @@ properties:
 
   interrupt-controller:
     type: object
-    additionalProperties: false
-    description: Describes the CPU's local interrupt controller
-
-    properties:
-      '#interrupt-cells':
-        const: 1
-
-      compatible:
-        oneOf:
-          - items:
-              - const: andestech,cpu-intc
-              - const: riscv,cpu-intc
-          - const: riscv,cpu-intc
-
-      interrupt-controller: true
-
-    required:
-      - '#interrupt-cells'
-      - compatible
-      - interrupt-controller
+    $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#
 
   cpu-idle-states:
     $ref: /schemas/types.yaml#/definitions/phandle-array
-- 
2.34.1