linux-kernel - [PATCH 0/9] AMD MCA interrupts rework

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Date: Thu, 23 May 2024 10:56:32 -0500
From: Yazen Ghannam <yazen.ghannam@....com>
To: <linux-edac@...r.kernel.org>
CC: <linux-kernel@...r.kernel.org>, <tony.luck@...el.com>, <x86@...nel.org>,
	<avadhut.naik@....com>, <john.allen@....com>, Yazen Ghannam
	<yazen.ghannam@....com>
Subject: [PATCH 0/9] AMD MCA interrupts rework

Hi all,

This set unifies the AMD MCA interrupt handlers with common MCA code.
The goal is to avoid duplicating functionality like reading and clearing
MCA banks.

Patches 1-3 are minor changes for issues found during testing.

Patches 4-9 are revised work of patches 6-12 from the following set:
https://lkml.kernel.org/r/20240404151359.47970-1-yazen.ghannam@amd.com

In addition to addressing review comments, I tried to reduce the amount
of refactoring to only what is functionally needed for fixes and
features. I still want to do a broader clean up, but I think that can
come later.

Patch 7 has a minor merge conflict with the following set:
https://lkml.kernel.org/r/20240521125434.1555845-1-yazen.ghannam@amd.com

The sets do not depend on each other, so I thought to keep them
separate. But I can rebase this one on the other, if needed.

Thanks,
Yazen

Yazen Ghannam (9):
  x86/mce/inject: Only write MCA_MISC with user-set value
  x86/mce: Remove unused variable and return value in
    machine_check_poll()
  x86/mce: Increment MCP count only for timer calls
  x86/mce: Move machine_check_poll() status checks to helper functions
  x86/mce: Skip AMD threshold init if no threshold banks found
  x86/mce: Unify AMD THR handler with MCA Polling
  x86/mce: Unify AMD DFR handler with MCA Polling
  x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems
  x86/mce/amd: Support SMCA Corrected Error Interrupt

 arch/x86/include/asm/mce.h         |   3 +-
 arch/x86/kernel/cpu/mce/amd.c      | 274 +++++++++--------------------
 arch/x86/kernel/cpu/mce/core.c     | 143 +++++++++------
 arch/x86/kernel/cpu/mce/inject.c   |   8 +-
 arch/x86/kernel/cpu/mce/internal.h |   7 +-
 5 files changed, 186 insertions(+), 249 deletions(-)


base-commit: 108c6494bdf1dfeaefc0a506e2f471aa92fafdd6
-- 
2.34.1