linux-kernel - Re: [PATCH 1/6] dt-bindings: ti, sci: Add property for partial-io-wakeup-sources

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Message-ID: <20240524004346.szrp7iiec2nhgvle@denatured>
Date: Thu, 23 May 2024 19:43:46 -0500
From: Nishanth Menon <nm@...com>
To: Markus Schneider-Pargmann <msp@...libre.com>
CC: Tero Kristo <kristo@...nel.org>, Santosh Shilimkar <ssantosh@...nel.org>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Vignesh Raghavendra <vigneshr@...com>,
        Vibhore Vardhan <vibhore@...com>, Kevin Hilman <khilman@...libre.com>,
        Dhruva Gole <d-gole@...com>, <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/6] dt-bindings: ti, sci: Add property for
 partial-io-wakeup-sources

On 10:02-20240523, Markus Schneider-Pargmann wrote:
> Add a property with an array of phandles to devices that have pins that
> are capable to wakeup the SoC from Partial-IO. In Partial-IO everything
> is powered off including the DDR. Only pins belonging to a couple of
> devices are active and wakeup the system on activity.
> 
> Signed-off-by: Markus Schneider-Pargmann <msp@...libre.com>
> ---
>  Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml
> index 7f06b1080244..c8ed0dd4fee4 100644
> --- a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml
> +++ b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml
> @@ -61,6 +61,12 @@ properties:
>    mboxes:
>      minItems: 2
>  
> +  ti,partial-io-wakeup-sources:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    description: |
> +      List of phandles to devicetree nodes that can wakeup the SoC from the
> +      Partial IO poweroff mode.

I think the description needs a bunch of improvement here.

Can I use no board peripherals to be the phandle? say a GPIO expander
irq? This is not clear from the patch how peripherals and pins are
related?

We also need to warn readers that this capability is firmware driven and
not available on all SoC variants.

> +
>    ti,host-id:
>      $ref: /schemas/types.yaml#/definitions/uint32
>      description: |
> -- 
> 2.43.0
> 

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D