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Message-Id: <20240525-sc8180x-usb-mp-v1-8-60a904392438@quicinc.com>
Date: Sat, 25 May 2024 11:04:01 -0700
From: Bjorn Andersson <andersson@...nel.org>
To: Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Wesley Cheng <quic_wcheng@...cinc.com>,
Konrad Dybcio <konrad.dybcio@...aro.org>
Cc: linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, linux-usb@...r.kernel.org,
Bjorn Andersson <quic_bjorande@...cinc.com>
Subject: [PATCH 08/10] arm64: dts: qcom: sc8180x: Add USB MP controller and
phys
From: Bjorn Andersson <quic_bjorande@...cinc.com>
The SC8180X platform comes with a multiport DWC3 controller with two
ports, each connected to a pair of HighSpeed and QMP SuperSpeed PHYs.
Describe these blocks.
Signed-off-by: Bjorn Andersson <quic_bjorande@...cinc.com>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 146 ++++++++++++++++++++++++++++++++++
1 file changed, 146 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 9ef3fa40e1d8..0950dc7adb20 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -2511,6 +2511,34 @@ usb_sec_hsphy: phy@...3000 {
status = "disabled";
};
+ usb_mp0_hsphy: phy@...4000 {
+ compatible = "qcom,sc8180x-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
+ reg = <0 0x088e4000 0 0x400>;
+ #phy-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_MP0_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_mp1_hsphy: phy@...5000 {
+ compatible = "qcom,sc8180x-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
+ reg = <0 0x088e5000 0 0x400>;
+ #phy-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_MP1_BCR>;
+
+ status = "disabled";
+ };
+
usb_prim_qmpphy: phy@...9000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>,
@@ -2577,6 +2605,54 @@ usb_prim_dpphy: dp-phy@...a200 {
};
};
+ usb_mp0_qmpphy: phy@...b000 {
+ compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
+ reg = <0 0x088eb000 0 0x1000>;
+
+ clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
+
+ resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
+ <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
+ reset-names = "phy", "phy_phy";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "usb2_phy0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_mp1_qmpphy: phy@...c000 {
+ compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
+ reg = <0 0x088ec000 0 0x1000>;
+
+ clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
+
+ resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
+ <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
+ reset-names = "phy", "phy_phy";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "usb2_phy1_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
usb_sec_qmpphy: phy@...e000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
reg = <0 0x088ee000 0 0x18c>,
@@ -2662,6 +2738,76 @@ gem_noc: interconnect@...0000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ usb_mp: usb@...8800 {
+ compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
+ reg = <0 0x0a4f8800 0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_SLEEP_CLK>,
+ <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB3_SEC_CLKREF_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MP_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 59 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 46 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 71 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 68 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event_1", "pwr_event_2",
+ "hs_phy_1", "hs_phy_2",
+ "dp_hs_phy_1", "dm_hs_phy_1",
+ "dp_hs_phy_2", "dm_hs_phy_2",
+ "ss_phy_1", "ss_phy_2";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+
+ resets = <&gcc GCC_USB30_MP_BCR>;
+
+ status = "disabled";
+
+ usb_mp_dwc3: usb@...0000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a400000 0 0xcd00>;
+ interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x60 0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ phys = <&usb_mp0_hsphy>,
+ <&usb_mp0_qmpphy>,
+ <&usb_mp1_hsphy>,
+ <&usb_mp1_qmpphy>;
+ phy-names = "usb2-0",
+ "usb3-0",
+ "usb2-1",
+ "usb3-1";
+ dr_mode = "host";
+ };
+ };
+
usb_prim: usb@...8800 {
compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
--
2.43.0
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