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Message-ID: <20240527063015.263748-1-danishanwar@ti.com>
Date: Mon, 27 May 2024 12:00:15 +0530
From: MD Danish Anwar <danishanwar@...com>
To: Diogo Ivo <diogo.ivo@...mens.com>, Andrew Lunn <andrew@...n.ch>,
Paolo
Abeni <pabeni@...hat.com>, Jakub Kicinski <kuba@...nel.org>,
Eric Dumazet
<edumazet@...gle.com>,
"David S. Miller" <davem@...emloft.net>
CC: <linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <srk@...com>,
Vignesh Raghavendra
<vigneshr@...com>,
Roger Quadros <rogerq@...nel.org>,
MD Danish Anwar
<danishanwar@...com>,
Florian Fainelli <f.fainelli@...il.com>
Subject: [PATCH net v2] net: ti: icssg-prueth: Fix start counter for ft1 filter
The start counter for FT1 filter is wrongly set to 0 in the driver.
FT1 is used for source address violation (SAV) check and source address
starts at Byte 6 not Byte 0. Fix this by changing start counter to
ETH_ALEN in icssg_ft1_set_mac_addr().
Fixes: e9b4ece7d74b ("net: ti: icssg-prueth: Add Firmware config and classification APIs.")
Signed-off-by: MD Danish Anwar <danishanwar@...com>
---
Cc: Florian Fainelli <f.fainelli@...il.com>
Changes from v1 to v2:
*) Using ETH_ALEN instead of hardcoding the values to 6 as suggested by
Florian Fainelli <f.fainelli@...il.com>
v1: https://lore.kernel.org/all/20240524093719.68353-1-danishanwar@ti.com/
drivers/net/ethernet/ti/icssg/icssg_classifier.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/ti/icssg/icssg_classifier.c b/drivers/net/ethernet/ti/icssg/icssg_classifier.c
index 79ba47bb3602..f7d21da1a0fb 100644
--- a/drivers/net/ethernet/ti/icssg/icssg_classifier.c
+++ b/drivers/net/ethernet/ti/icssg/icssg_classifier.c
@@ -455,7 +455,7 @@ void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr)
{
const u8 mask_addr[] = { 0, 0, 0, 0, 0, 0, };
- rx_class_ft1_set_start_len(miig_rt, slice, 0, 6);
+ rx_class_ft1_set_start_len(miig_rt, slice, ETH_ALEN, ETH_ALEN);
rx_class_ft1_set_da(miig_rt, slice, 0, mac_addr);
rx_class_ft1_set_da_mask(miig_rt, slice, 0, mask_addr);
rx_class_ft1_cfg_set_type(miig_rt, slice, 0, FT1_CFG_TYPE_EQ);
base-commit: 0b4f5add9fa59bfd42c1030f572db2e4c395181b
--
2.34.1
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