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Message-Id: <20240527-sg2002-v1-4-1b6cb38ce8f4@bootlin.com>
Date: Mon, 27 May 2024 12:28:20 +0200
From: Thomas Bonnefille <thomas.bonnefille@...tlin.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Paul Walmsley <paul.walmsley@...ive.com>, 
 Chen Wang <unicorn_wang@...look.com>, Inochi Amaoto <inochiama@...look.com>, 
 Chao Wei <chao.wei@...hgo.com>
Cc: Albert Ou <aou@...s.berkeley.edu>, Palmer Dabbelt <palmer@...belt.com>, 
 Samuel Holland <samuel.holland@...ive.com>, 
 Thomas Gleixner <tglx@...utronix.de>, 
 Daniel Lezcano <daniel.lezcano@...aro.org>, 
 Thomas Petazzoni <thomas.petazzoni@...tlin.com>, 
 Miquèl Raynal <miquel.raynal@...tlin.com>, 
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
 linux-riscv@...ts.infradead.org, 
 Thomas Bonnefille <thomas.bonnefille@...tlin.com>
Subject: [PATCH 4/5] riscv: dts: sophgo: Add initial SG2002 SoC device tree

Add initial device tree for the SG2002 RISC-V SoC by SOPHGO.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@...tlin.com>
---
 arch/riscv/boot/dts/sophgo/sg2002.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
new file mode 100644
index 000000000000..b266357cb5c0
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@...tlin.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx.dtsi"
+
+/ {
+	compatible = "sophgo,sg2002";
+
+	memory@...00000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>;
+	};
+};
+
+&plic {
+	compatible = "sophgo,sg2002-plic", "thead,c900-plic";
+};
+
+&clint {
+	compatible = "sophgo,sg2002-clint", "thead,c900-clint";
+};
+
+&clk {
+	compatible = "sophgo,sg2000-clk";
+};

-- 
2.45.1


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