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Message-ID: <ZlX8u6V6l3ZwurI0@pengutronix.de>
Date: Tue, 28 May 2024 17:48:11 +0200
From: Oleksij Rempel <o.rempel@...gutronix.de>
To: Sebastien Laveze <slaveze@...rtandconnective.com>
Cc: Abel Vesa <abelvesa@...nel.org>, Peng Fan <peng.fan@....com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, Lee Jones <lee@...nel.org>,
imx@...ts.linux.dev, linux-kernel@...r.kernel.org,
Abel Vesa <abel.vesa@...aro.org>, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH] clk: imx: imx6ul: fix default parent for enet*_ref_sel
On Tue, May 28, 2024 at 05:14:33PM +0200, Sebastien Laveze wrote:
> The clk_set_parent for "enet1_ref_sel" and "enet2_ref_sel" are
> incorrect, therefore the original requirements to have "enet_clk_ref" as
> output sourced by iMX ENET PLL as a default config is not met.
>
> Only "enet[1,2]_ref_125m" "enet[1,2]_ref_pad" are possible parents for
> "enet1_ref_sel" and "enet2_ref_sel".
>
> This was observed as a regression using a custom device tree which was
> expecting this default config.
>
> This can be fixed at the device tree level but having a default config
> matching the original behavior (before refclock mux) will avoid breaking
> existing configs.
>
> Fixes: 4e197ee880c2 ("clk: imx6ul: add ethernet refclock mux support")
> Link: https://lore.kernel.org/lkml/20230306020226.GC143566@dragon/T/
> Signed-off-by: Sebastien Laveze <slaveze@...rtandconnective.com>
Reviewed-by: Oleksij Rempel <o.rempel@...gutronix.de>
Thank you.
> ---
> drivers/clk/imx/clk-imx6ul.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
> index f9394e94f69d..05c7a82b751f 100644
> --- a/drivers/clk/imx/clk-imx6ul.c
> +++ b/drivers/clk/imx/clk-imx6ul.c
> @@ -542,8 +542,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
>
> clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk);
>
> - clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk);
> - clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk);
> + clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET1_REF_125M]->clk);
> + clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF_125M]->clk);
>
> imx_register_uart_clocks();
> }
> --
> 2.34.1
>
>
>
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