linux-kernel - [tip: x86/cpu] x86/platform/intel-mid: Switch to new Intel CPU model defines

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [day] [month] [year] [list]

Message-ID: <171691950792.10875.1205586224750520432.tip-bot2@tip-bot2>
Date: Tue, 28 May 2024 18:05:07 -0000
From: "tip-bot2 for Tony Luck" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Tony Luck <tony.luck@...el.com>, Dave Hansen <dave.hansen@...ux.intel.com>,
 Andy Shevchenko <andy@...nel.org>, x86@...nel.org,
 linux-kernel@...r.kernel.org
Subject:
 [tip: x86/cpu] x86/platform/intel-mid: Switch to new Intel CPU model defines

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     2cf615a4519b29a3ad283883d7638279ec1e6b44
Gitweb:        https://git.kernel.org/tip/2cf615a4519b29a3ad283883d7638279ec1e6b44
Author:        Tony Luck <tony.luck@...el.com>
AuthorDate:    Tue, 21 May 2024 09:10:01 -07:00
Committer:     Dave Hansen <dave.hansen@...ux.intel.com>
CommitterDate: Tue, 28 May 2024 10:59:02 -07:00

x86/platform/intel-mid: Switch to new Intel CPU model defines

New CPU #defines encode vendor and family as well as model.

N.B. Drop Haswell. CPU model 0x3C was included by mistake
in upstream code.

Signed-off-by: Tony Luck <tony.luck@...el.com>
Signed-off-by: Dave Hansen <dave.hansen@...ux.intel.com>
Acked-by: Andy Shevchenko <andy@...nel.org>
Link: https://lore.kernel.org/all/20240521161002.12866-1-tony.luck%40intel.com
---
 arch/x86/platform/intel-mid/intel-mid.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 7be71c2..f83bbe0 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -22,6 +22,7 @@
 #include <asm/mpspec_def.h>
 #include <asm/hw_irq.h>
 #include <asm/apic.h>
+#include <asm/cpu_device_id.h>
 #include <asm/io_apic.h>
 #include <asm/intel-mid.h>
 #include <asm/io.h>
@@ -55,9 +56,8 @@ static void __init intel_mid_time_init(void)
 
 static void intel_mid_arch_setup(void)
 {
-	switch (boot_cpu_data.x86_model) {
-	case 0x3C:
-	case 0x4A:
+	switch (boot_cpu_data.x86_vfm) {
+	case INTEL_ATOM_SILVERMONT_MID:
 		x86_platform.legacy.rtc = 1;
 		break;
 	default: