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Message-ID: <cfc138b2-9c12-4b71-b60c-c098cc1f8c06@quicinc.com>
Date: Tue, 28 May 2024 15:59:56 -0700
From: Jessica Zhang <quic_jesszhan@...cinc.com>
To: Jun Nie <jun.nie@...aro.org>, Rob Clark <robdclark@...il.com>,
"Abhinav
Kumar" <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov
<dmitry.baryshkov@...aro.org>,
Sean Paul <sean@...rly.run>,
Marijn Suijten
<marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, "Daniel
Vetter" <daniel@...ll.ch>,
Vinod Koul <vkoul@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
<freedreno@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 3/6] drm/msm/dpu: enable compression bit in cfg2 for
DSC
On 5/27/2024 7:21 AM, Jun Nie wrote:
> Enable compression bit in cfg2 register for DSC in the DSI case
>
> Signed-off-by: Jun Nie <jun.nie@...aro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index f97221423249..34bfcfba3df2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -177,6 +177,10 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
> if (p->wide_bus_en && !dp_intf)
> data_width = p->width >> 1;
>
> + /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */
> + if (p->compression_en && !dp_intf)
> + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
Hi Jun,
The DSC/DCE enablement registers were only moved to INTF in DPU 7.x and
later.
We should probably add some MDSS version check similar to what command
mode INTF does here [1]
Thanks,
Jessica Zhang
> +
> hsync_data_start_x = hsync_start_x;
> hsync_data_end_x = hsync_start_x + data_width - 1;
>
>
> --
> 2.34.1
>
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