linux-kernel - Re: (subset) [PATCH v7 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P

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Message-ID: <171686715168.523693.9031947967155773855.b4-ty@kernel.org>
Date: Mon, 27 May 2024 22:32:30 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: krzysztof.kozlowski+dt@...aro.org,
	conor+dt@...nel.org,
	konrad.dybcio@...aro.org,
	manivannan.sadhasivam@...aro.org,
	robh@...nel.org,
	Mrinmay Sarkar <quic_msarkar@...cinc.com>
Cc: quic_shazhuss@...cinc.com,
	quic_nitegupt@...cinc.com,
	quic_ramkri@...cinc.com,
	quic_nayiluri@...cinc.com,
	quic_krichai@...cinc.com,
	quic_vbadigan@...cinc.com,
	quic_schintav@...cinc.com,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof Wilczyński <kw@...ux.com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	linux-arm-msm@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-pci@...r.kernel.org
Subject: Re: (subset) [PATCH v7 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P


On Mon, 11 Mar 2024 19:41:34 +0530, Mrinmay Sarkar wrote:
> Due to some hardware changes, SA8775P has set the NO_SNOOP attribute
> in its TLP for all the PCIe controllers. NO_SNOOP attribute when set,
> the requester is indicating that no cache coherency issues exist for
> the addressed memory on the host i.e., memory is not cached. But in
> reality, requester cannot assume this unless there is a complete
> control/visibility over the addressed memory on the host.
> 
> [...]

Applied, thanks!

[3/3] arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent
      commit: 4b220c6fa9f379cb8803dbca73ae1f4128dfa5c8

Best regards,
-- 
Bjorn Andersson <andersson@...nel.org>