linux-kernel - Re: [PATCH V3 8/8] arm64: dts: qcom: sm4450: add camera, display and gpu clock controller

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Message-ID: <rlpiuzfhjzssp2bt7bbltn2hoofw2oxga7q4tl26qs5ctvjl24@boejq5zyqmfo>
Date: Tue, 28 May 2024 16:15:35 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Ajit Pandey <quic_ajipan@...cinc.com>
Cc: Michael Turquette <mturquette@...libre.com>, 
	Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, 
	Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>, 
	Vinod Koul <vkoul@...nel.org>, Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>, 
	linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Taniya Das <quic_tdas@...cinc.com>, 
	Jagadeesh Kona <quic_jkona@...cinc.com>, Imran Shaik <quic_imrashai@...cinc.com>, 
	Satya Priya Kakitapalli <quic_skakitap@...cinc.com>
Subject: Re: [PATCH V3 8/8] arm64: dts: qcom: sm4450: add camera, display and
 gpu clock controller

On Tue, May 28, 2024 at 05:12:54PM +0530, Ajit Pandey wrote:
> Add device node for camera, display and graphics clock controller on
> Qualcomm SM4450 platform.
> 
> Signed-off-by: Ajit Pandey <quic_ajipan@...cinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm4450.dtsi | 38 ++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> index 8d75c4f9731c..ef448e13b8a0 100644
> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> @@ -4,7 +4,10 @@
>   */
>  
>  #include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/clock/qcom,sm4450-camcc.h>
> +#include <dt-bindings/clock/qcom,sm4450-dispcc.h>
>  #include <dt-bindings/clock/qcom,sm4450-gcc.h>
> +#include <dt-bindings/clock/qcom,sm4450-gpucc.h>
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> @@ -388,6 +391,41 @@ gcc: clock-controller@...000 {
>  				 <0>;
>  		};
>  
> +		gpucc: clock-controller@...0000 {
> +			compatible = "qcom,sm4450-gpucc";
> +			reg = <0 0x3d90000 0 0xa000>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> +				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
> +		camcc: clock-controller@...0000 {
> +			compatible = "qcom,sm4450-camcc";
> +			reg = <0x0 0xade0000 0x0 0x20000>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_CAMERA_AHB_CLK>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};

Please keep all the nodes sorted using the device address.

> +
> +		dispcc: clock-controller@...0000 {
> +			compatible = "qcom,sm4450-dispcc";
> +			reg = <0 0x0af00000 0 0x20000>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&rpmhcc RPMH_CXO_CLK_A>,
> +				 <&gcc GCC_DISP_AHB_CLK>,
> +				 <&sleep_clk>,
> +				 <0>,
> +				 <0>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
>  		qupv3_id_0: geniqup@...000 {
>  			compatible = "qcom,geni-se-qup";
>  			reg = <0x0 0x00ac0000 0x0 0x2000>;
> -- 
> 2.25.1
> 

-- 
With best wishes
Dmitry