linux-kernel - [PATCH RFC 3/6] riscv: perf: Add Control Transfer Records extension parsing

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Message-Id: <20240529185337.182722-4-rkanwal@rivosinc.com>
Date: Wed, 29 May 2024 19:53:34 +0100
From: Rajnesh Kanwal <rkanwal@...osinc.com>
To: linux-kernel@...r.kernel.org
Cc: linux-perf-users@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	adrian.hunter@...el.com,
	alexander.shishkin@...ux.intel.com,
	ajones@...tanamicro.com,
	anup@...infault.org,
	acme@...nel.org,
	atishp@...osinc.com,
	beeman@...osinc.com,
	brauner@...nel.org,
	conor@...nel.org,
	heiko@...ech.de,
	irogers@...gle.com,
	mingo@...hat.com,
	james.clark@....com,
	renyu.zj@...ux.alibaba.com,
	jolsa@...nel.org,
	jisheng.teoh@...rfivetech.com,
	palmer@...belt.com,
	tech-control-transfer-records@...ts.riscv.org,
	will@...nel.org,
	kaiwenxue1@...il.com,
	Rajnesh Kanwal <rkanwal@...osinc.com>
Subject: [PATCH RFC 3/6] riscv: perf: Add Control Transfer Records extension parsing

Adding CTR extension in ISA extension map to lookup for extension
availability.

Signed-off-by: Rajnesh Kanwal <rkanwal@...osinc.com>
---
 arch/riscv/include/asm/hwcap.h | 4 ++++
 arch/riscv/kernel/cpufeature.c | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index b8cc459ee8a4..aff5ef398671 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -86,6 +86,8 @@
 #define RISCV_ISA_EXT_SSCCFG            77
 #define RISCV_ISA_EXT_SMCDELEG          78
 #define RISCV_ISA_EXT_SMCNTRPMF         79
+#define RISCV_ISA_EXT_SMCTR             80
+#define RISCV_ISA_EXT_SSCTR             81
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
@@ -95,9 +97,11 @@
 #ifdef CONFIG_RISCV_M_MODE
 #define RISCV_ISA_EXT_SxAIA		RISCV_ISA_EXT_SMAIA
 #define RISCV_ISA_EXT_SxCSRIND		RISCV_ISA_EXT_SMCSRIND
+#define RISCV_ISA_EXT_SxCTR		RISCV_ISA_EXT_SMCTR
 #else
 #define RISCV_ISA_EXT_SxAIA		RISCV_ISA_EXT_SSAIA
 #define RISCV_ISA_EXT_SxCSRIND		RISCV_ISA_EXT_SSCSRIND
+#define RISCV_ISA_EXT_SxCTR		RISCV_ISA_EXT_SSCTR
 #endif
 
 #endif /* _ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index d1fb6a8c5492..4334d822b2f2 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -298,6 +298,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
 	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
 	__RISCV_ISA_EXT_DATA(smcdeleg, RISCV_ISA_EXT_SMCDELEG),
+	__RISCV_ISA_EXT_DATA(smctr, RISCV_ISA_EXT_SMCTR),
 	__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
 	__RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF),
 	__RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND),
@@ -305,6 +306,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND),
 	__RISCV_ISA_EXT_DATA(ssccfg, RISCV_ISA_EXT_SSCCFG),
 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
+	__RISCV_ISA_EXT_DATA(ssctr, RISCV_ISA_EXT_SSCTR),
 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
 	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
 	__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
-- 
2.34.1