linux-kernel - Re: [PATCH 1/2] HID: intel-ish-hid: fix cache management mistake

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Date: Wed, 29 May 2024 09:06:17 +0200
From: "Arnd Bergmann" <arnd@...db.de>
To: "Lixu Zhang" <lixu.zhang@...el.com>, "Arnd Bergmann" <arnd@...nel.org>,
 "srinivas.pandruvada@...ux.intel.com" <srinivas.pandruvada@...ux.intel.com>,
 "Jiri Kosina" <jikos@...nel.org>, "Benjamin Tissoires" <bentiss@...nel.org>
Cc: "linux-input@...r.kernel.org" <linux-input@...r.kernel.org>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] HID: intel-ish-hid: fix cache management mistake

On Wed, May 29, 2024, at 08:46, Zhang, Lixu wrote:
>>
>>-#include <linux/cacheflush.h>
>> #include <linux/container_of.h>
>> #include <linux/dev_printk.h>
>> #include <linux/dma-mapping.h>
>>@@ -175,10 +174,11 @@ static int prepare_dma_bufs(struct ishtp_device
>>*dev,
>> 			return -ENOMEM;
>>
>> 		fragment->fragment_tbl[i].ddr_adrs =
>>cpu_to_le64(dma_addr);
>>+
>>+		memcpy(dma_bufs[i], ish_fw->data + offset, fragment-
>>>fragment_tbl[i].length);
> fragment->fragment_tbl[i].length was used before assignment.
> 
>>+		dma_wmb();
> I tested it on the platform, but it didn't wok.
>

What behavior do you see instead? If the manual cache
flush works around a bug, that would indicate that the
device itself is not coherent and the dma_alloc_coherent()
in the architecture is broken.

     Arnd