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Message-Id: <b1fc49269919c7d6c2e5c607ae29d1a6f2ab40d2.1716965617.git.ysato@users.sourceforge.jp>
Date: Wed, 29 May 2024 17:00:59 +0900
From: Yoshinori Sato <ysato@...rs.sourceforge.jp>
To: linux-sh@...r.kernel.org
Cc: Yoshinori Sato <ysato@...rs.sourceforge.jp>,
Damien Le Moal <dlemoal@...nel.org>,
Niklas Cassel <cassel@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
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Krzysztof Wilczyński <kw@...ux.com>,
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Daniel Lezcano <daniel.lezcano@...aro.org>,
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Sergey Shtylyov <s.shtylyov@....ru>,
Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>,
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linux-kernel@...r.kernel.org,
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dri-devel@...ts.freedesktop.org,
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Subject: [DO NOT MERGE v8 13/36] dt-bindings: clock: sh7750-cpg: Add renesas,sh7750-cpg header.
SH7750 CPG Clock output define.
Signed-off-by: Yoshinori Sato <ysato@...rs.sourceforge.jp>
---
.../bindings/clock/renesas,sh7750-cpg.yaml | 107 ++++++++++++++++++
include/dt-bindings/clock/sh7750-cpg.h | 26 +++++
2 files changed, 133 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
create mode 100644 include/dt-bindings/clock/sh7750-cpg.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
new file mode 100644
index 000000000000..0cdcab6fb4bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7750/7751 Clock Pulse Generator (CPG)
+
+maintainers:
+ - Yoshinori Sato <ysato@...rs.sourceforge.jp>
+
+description:
+ The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
+ includes PLLs, and variable ratio dividers.
+
+ The CPG may also provide a Clock Domain for SoC devices, in combination with
+ the CPG Module Stop (MSTP) Clocks.
+
+properties:
+ compatible:
+ enum:
+ - renesas,sh7750-cpg # SH7750
+ - renesas,sh7750s-cpg # SH775S
+ - renesas,sh7750r-cpg # SH7750R
+ - renesas,sh7751-cpg # SH7751
+ - renesas,sh7751r-cpg # SH7751R
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names: true
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: extal
+
+ '#clock-cells':
+ const: 1
+
+ renesas,mode:
+ description: Board-specific settings of the MD[0-2] pins on SoC
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 6
+
+ '#power-domain-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,sh7750-cpg
+ - renesas,sh7750s-cpg
+ then:
+ properties:
+ reg:
+ maxItems: 1
+ reg-names:
+ items:
+ - const: FRQCR
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,sh7750r-cpg
+ - renesas,sh7751-cpg
+ - renesas,sh7751r-cpg
+ then:
+ properties:
+ reg:
+ minItems: 2
+ reg-names:
+ items:
+ - const: FRQCR
+ - const: CLKSTP00
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/sh7750-cpg.h>
+ cpg: clock-controller@...00000 {
+ compatible = "renesas,sh7751r-cpg";
+ reg = <0xffc00000 20>, <0xfe0a0000 16>;
+ reg-names = "FRQCR", "CLKSTP00";
+ clocks = <&extal>;
+ clock-names = "extal";
+ renesas,mode = <0>;
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+ };
diff --git a/include/dt-bindings/clock/sh7750-cpg.h b/include/dt-bindings/clock/sh7750-cpg.h
new file mode 100644
index 000000000000..ec267be91adf
--- /dev/null
+++ b/include/dt-bindings/clock/sh7750-cpg.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SH7750_H__
+#define __DT_BINDINGS_CLOCK_SH7750_H__
+
+#define SH7750_CPG_PLLOUT 0
+
+#define SH7750_CPG_PCK 1
+#define SH7750_CPG_BCK 2
+#define SH7750_CPG_ICK 3
+
+#define SH7750_MSTP_SCI 4
+#define SH7750_MSTP_RTC 5
+#define SH7750_MSTP_TMU012 6
+#define SH7750_MSTP_SCIF 7
+#define SH7750_MSTP_DMAC 8
+#define SH7750_MSTP_UBC 9
+#define SH7750_MSTP_SQ 10
+#define SH7750_CSTP_INTC 11
+#define SH7750_CSTP_TMU34 12
+#define SH7750_CSTP_PCIC 13
+
+#endif
--
2.39.2
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