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Date: Wed, 29 May 2024 17:01:14 +0900
From: Yoshinori Sato <ysato@...rs.sourceforge.jp>
To: linux-sh@...r.kernel.org
Cc: Yoshinori Sato <ysato@...rs.sourceforge.jp>,
	Damien Le Moal <dlemoal@...nel.org>,
	Niklas Cassel <cassel@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>,
	David Airlie <airlied@...il.com>,
	Daniel Vetter <daniel@...ll.ch>,
	Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
	Maxime Ripard <mripard@...nel.org>,
	Thomas Zimmermann <tzimmermann@...e.de>,
	Thomas Gleixner <tglx@...utronix.de>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof Wilczyński <kw@...ux.com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Jiri Slaby <jirislaby@...nel.org>,
	Magnus Damm <magnus.damm@...il.com>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Rich Felker <dalias@...c.org>,
	John Paul Adrian Glaubitz <glaubitz@...sik.fu-berlin.de>,
	Lee Jones <lee@...nel.org>,
	Helge Deller <deller@....de>,
	Heiko Stuebner <heiko.stuebner@...rry.de>,
	Neil Armstrong <neil.armstrong@...aro.org>,
	Chris Morgan <macromorgan@...mail.com>,
	Sebastian Reichel <sre@...nel.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	Arnd Bergmann <arnd@...db.de>,
	Masahiro Yamada <masahiroy@...nel.org>,
	Baoquan He <bhe@...hat.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Guenter Roeck <linux@...ck-us.net>,
	Kefeng Wang <wangkefeng.wang@...wei.com>,
	Stephen Rothwell <sfr@...b.auug.org.au>,
	Azeem Shaikh <azeemshaikh38@...il.com>,
	Guo Ren <guoren@...nel.org>,
	Max Filippov <jcmvbkbc@...il.com>,
	Jernej Skrabec <jernej.skrabec@...il.com>,
	Herve Codina <herve.codina@...tlin.com>,
	Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
	Anup Patel <apatel@...tanamicro.com>,
	Jacky Huang <ychuang3@...oton.com>,
	Hugo Villeneuve <hvilleneuve@...onoff.com>,
	Jonathan Corbet <corbet@....net>,
	Wolfram Sang <wsa+renesas@...g-engineering.com>,
	Uwe Kleine-König <u.kleine-koenig@...gutronix.de>,
	Christophe JAILLET <christophe.jaillet@...adoo.fr>,
	Sam Ravnborg <sam@...nborg.org>,
	Javier Martinez Canillas <javierm@...hat.com>,
	Sergey Shtylyov <s.shtylyov@....ru>,
	Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>,
	linux-ide@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org,
	linux-clk@...r.kernel.org,
	dri-devel@...ts.freedesktop.org,
	linux-pci@...r.kernel.org,
	linux-serial@...r.kernel.org,
	linux-fbdev@...r.kernel.org
Subject: [DO NOT MERGE v8 28/36] sh: SH7751R SoC Internal peripheral definition dtsi.

SH7751R internal peripherals device tree.

Signed-off-by: Yoshinori Sato <ysato@...rs.sourceforge.jp>
---
 arch/sh/boot/dts/sh7751r.dtsi | 105 ++++++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644 arch/sh/boot/dts/sh7751r.dtsi

diff --git a/arch/sh/boot/dts/sh7751r.dtsi b/arch/sh/boot/dts/sh7751r.dtsi
new file mode 100644
index 000000000000..61b2af5bebde
--- /dev/null
+++ b/arch/sh/boot/dts/sh7751r.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the SH7751R SoC
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/sh7750-cpg.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "renesas,sh4", "renesas,sh2";
+			device_type = "cpu";
+			reg = <0>;
+			clocks = <&cpg SH7750_CPG_ICK>;
+			clock-names = "ick";
+			icache-size = <16384>;
+			icache-line-size = <32>;
+			dcache-size = <32768>;
+			dcache-line-size = <32>;
+		};
+	};
+
+	extal: oscillator {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+		clock-output-names = "extal";
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&shintc>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		cpg: clock-controller@...00000 {
+			#clock-cells = <1>;
+			#power-domain-cells = <0>;
+			compatible = "renesas,sh7751r-cpg";
+			clocks = <&extal>;
+			clock-names = "extal";
+			reg = <0xffc00000 20>, <0xfe0a0000 16>;
+			reg-names = "FRQCR", "CLKSTP00";
+			renesas,mode = <0>;
+		};
+
+		shintc: interrupt-controller@...00000 {
+			compatible = "renesas,sh7751-intc";
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0xffd00000 20>, <0xfe080000 128>;
+			reg-names = "ICR", "INTPRI00";
+		};
+
+		/* sci0 is rarely used, so it is not defined here. */
+		scif1: serial@...80000 {
+			compatible = "renesas,scif-sh7751", "renesas,scif";
+			reg = <0xffe80000 0x100>;
+			interrupts = <0x700>,
+				     <0x720>,
+				     <0x760>,
+				     <0x740>;
+			interrupt-names = "eri", "rxi", "txi", "bri";
+			clocks = <&cpg SH7750_MSTP_SCIF>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		/* Normally ch0 and ch1 are used, so we will define ch0 to ch2 here. */
+		tmu0: timer@...80000 {
+			compatible = "renesas,tmu-sh7750", "renesas,tmu";
+			reg = <0xffd80000 12>;
+			interrupts = <0x400>,
+				     <0x420>,
+				     <0x440>,
+				     <0x460>;
+			interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
+			clocks = <&cpg SH7750_MSTP_TMU012>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			#renesas,channels = <3>;
+		};
+
+		pcic: pci@...00000 {
+			compatible = "renesas,sh7751-pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			bus-range = <0 0>;
+			reg = <0xfe200000 0x0400>,
+			      <0xff800000 0x0100>;
+			status = "disabled";
+		};
+	};
+};
-- 
2.39.2


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