lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <8a41d875-8e6c-43da-90c7-0547648f214a@axis.com>
Date: Thu, 30 May 2024 10:02:40 +0200
From: Amna Waseem <Amna.Waseem@...s.com>
To: Guenter Roeck <linux@...ck-us.net>, Conor Dooley <conor@...nel.org>
Cc: Jean Delvare <jdelvare@...e.com>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Krzysztof Kozlowski <krzk@...nel.org>,
 linux-hwmon@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, kernel@...s.com
Subject: Re: [PATCH v2 1/2] dt-bindings: hwmon: ti,ina2xx: Add
 ti,alert-polarity property

On 5/29/24 18:20, Guenter Roeck wrote:
> On 5/29/24 09:17, Conor Dooley wrote:
>> On Wed, May 29, 2024 at 11:47:44AM +0200, Amna Waseem wrote:
>>> Add a property to the binding to configure the Alert Polarity.
>>> Alert pin is asserted based on the value of Alert Polarity bit of
>>> Mask/Enable register. It is by default 0 which means Alert pin is
>>> configured to be active low open collector. Value of 1 maps to
>>> Inverted (active high open collector).
>>>
>>> Signed-off-by: Amna Waseem <Amna.Waseem@...s.com>
>>> ---
>>>   Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml | 9 +++++++++
>>>   1 file changed, 9 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml 
>>> b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml
>>> index df86c2c92037..5a16d2d94587 100644
>>> --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml
>>> +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml
>>> @@ -66,6 +66,14 @@ properties:
>>>       description: phandle to the regulator that provides the VS 
>>> supply typically
>>>         in range from 2.7 V to 5.5 V.
>>>   +  ti,alert-polarity:
>>> +    description: Alert polarity bit value of Mask/Enable register. 
>>> Alert pin is
>>> +      asserted based on the value of Alert polarity Bit. Default 
>>> value is Normal
>>> +      (0 which maps to active-low open collector). The other value 
>>> is Inverted
>>> +      (1 which maps to active-high open collector).
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    enum: [0, 1]
>>
>> There's no need for this to have a value, it's sufficient to be a flag
>> of "ti,alert-active-high". Present would mean active-high and absent
>> active-low. This has the added benefit the devicetree node being
>> understandable to a reader.
>>
>
> Agreed, makes sense. Even better, at the same time simplifies the code.
>
> Guenter
>
>
Agreed. Will do it in next patch

Amna


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ