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Message-ID: <20240530093621.1925863-4-a-bhatia1@ti.com>
Date: Thu, 30 May 2024 15:06:15 +0530
From: Aradhya Bhatia <a-bhatia1@...com>
To: Tomi Valkeinen <tomi.valkeinen@...asonboard.com>,
Andrzej Hajda
<andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>,
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Laurent Pinchart
<Laurent.pinchart@...asonboard.com>,
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Jernej
Skrabec <jernej.skrabec@...il.com>,
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<maarten.lankhorst@...ux.intel.com>,
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Sarha <jyri.sarha@....fi>,
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David
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CC: DRI Development List <dri-devel@...ts.freedesktop.org>,
Linux Kernel List
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Sam Ravnborg <sam@...nborg.org>, Thierry
Reding <treding@...dia.com>,
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Devarsh Thakkar <devarsht@...com>,
Jayesh
Choudhary <j-choudhary@...com>, Jai Luthra <j-luthra@...com>,
Aradhya Bhatia
<a-bhatia1@...com>
Subject: [PATCH v2 3/9] drm/bridge: cdns-dsi: Fix the link and phy init order
The order of init of DSI link and DSI phy is wrong. The DSI link needs
to be configured before the DSI phy is getting configured. Otherwise,
the D-Phy is unable to lock in on the incoming PLL Reference clock[0].
Fix the order of inits.
[0]: See section 12.6.5.7.3 "Start-up Procedure" in J721E SoC TRM
TRM Link: http://www.ti.com/lit/pdf/spruil1
Fixes: fced5a364dee ("drm/bridge: cdns: Convert to phy framework")
Signed-off-by: Aradhya Bhatia <a-bhatia1@...com>
---
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
index 42565e253b2d..371a3453970c 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
@@ -775,8 +775,8 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)
WARN_ON_ONCE(cdns_dsi_check_conf(dsi, mode, &dsi_cfg, false));
- cdns_dsi_hs_init(dsi);
cdns_dsi_init_link(dsi);
+ cdns_dsi_hs_init(dsi);
writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa),
dsi->regs + VID_HSIZE1);
--
2.34.1
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