linux-kernel - Re: [PATCH 5/6] arm64: dts: mediatek: mt8173: Fix MFG

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <4f20f130-c9ab-43ea-a758-e29d7be10db0@collabora.com>
Date: Thu, 30 May 2024 12:03:41 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Chen-Yu Tsai <wenst@...omium.org>, Frank Binns <frank.binns@...tec.com>,
 Matt Coster <matt.coster@...tec.com>,
 Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
 Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
 Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>
Cc: David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
 dri-devel@...ts.freedesktop.org, linux-clk@...r.kernel.org,
 devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 5/6] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power
 domain clock

Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> The MFG_ASYNC domain, which is likely associated to the whole MFG block,
> currently specifies clk26m as its domain clock. This is bogus, since the
> clock is an external crystal with no controls. Also, the MFG block has
> a independent CLK_TOP_AXI_MFG_IN_SEL clock, which according to the block
> diagram, gates access to the hardware registers. Having this one as the
> domain clock makes much more sense. This also fixes access to the MFGTOP
> registers.
> 
> Change the MFG_ASYNC domain clock to CLK_TOP_AXI_MFG_IN_SEL.
> 
> Fixes: 8b6562644df9 ("arm64: dts: mediatek: Add mt8173 power domain controller")
> Signed-off-by: Chen-Yu Tsai <wenst@...omium.org>

Just one question... what happens if there's no GPU support at all and this
power domain gets powered off?

I expect the answer to be "nothing", so I'm preventively giving you my

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>

...but if I'm wrong and the answer isn't exactly "nothing", then I still agree
with this commit, but only after removing the Fixes tag.

Cheers,
Angelo

> ---
>   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 3458be7f7f61..136b28f80cc2 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -497,7 +497,7 @@ power-domain@...173_POWER_DOMAIN_USB {
>   				};
>   				mfg_async: power-domain@...173_POWER_DOMAIN_MFG_ASYNC {
>   					reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
> -					clocks = <&clk26m>;
> +					clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>;
>   					clock-names = "mfg";
>   					#address-cells = <1>;
>   					#size-cells = <0>;