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Message-ID: <20240530-revisit-profanity-889f1bcae21a@spud>
Date: Thu, 30 May 2024 16:43:01 +0100
From: Conor Dooley <conor@...nel.org>
To: Chen-Yu Tsai <wenst@...omium.org>
Cc: Frank Binns <frank.binns@...tec.com>,
Matt Coster <matt.coster@...tec.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
dri-devel@...ts.freedesktop.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/6] dt-bindings: clock: mediatek: Add mt8173 mfgtop
On Thu, May 30, 2024 at 04:35:00PM +0800, Chen-Yu Tsai wrote:
> The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
> in the datasheet, that contains clock gates, some power sequence signal
> delays, and other unknown registers that get toggled when the GPU is
> powered on.
>
> The clock gates are exposed as clocks provided by a clock controller,
> while the power sequencing bits are exposed as one singular power domain.
>
> Signed-off-by: Chen-Yu Tsai <wenst@...omium.org>
> ---
> .../clock/mediatek,mt8173-mfgtop.yaml | 71 +++++++++++++++++++
> include/dt-bindings/clock/mt8173-clk.h | 7 ++
> 2 files changed, 78 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
> new file mode 100644
> index 000000000000..03c3c1f8cf75
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +
> +$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT8173 MFG TOP controller
> +
> +maintainers:
> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> +
> +description:
> + The MFG TOP glue layer controls various signals going to the MFG (GPU)
> + block on the MT8173.
> +
> +properties:
> + compatible:
> + const: mediatek,mt8173-mfgtop
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 4
minItems is not needed when minItems == maxItems.
> + maxItems: 4
> +
> + clock-names:
> + items:
> + - const: sys
> + - const: mem
> + - const: core
> + - const: clk26m
> +
> + power-domains:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> + '#power-domain-cells':
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - power-domains
> + - '#clock-cells'
> + - '#power-domain-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8173-clk.h>
> + #include <dt-bindings/power/mt8173-power.h>
> +
> + mfgtop: clock-controller@...ff000 {
The label here is used, so drop it.
Otherwise,
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Thanks,
Conor.
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