linux-kernel - Re: [PATCH] ARM: dts: ls1021a: add QUICC Engine node

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Message-ID: <3380831.44csPzL39Z@steina-w>
Date: Fri, 31 May 2024 08:32:44 +0200
From: Alexander Stein <alexander.stein@...tq-group.com>
To: Shawn Guo <shawnguo@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, linux-arm-kernel@...ts.infradead.org
Cc: Rasmus Villemoes <linux@...musvillemoes.dk>, linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, Esben Haabendal <esben@...nix.com>, Esben Haabendal <esben@...nix.com>
Subject: Re: [PATCH] ARM: dts: ls1021a: add QUICC Engine node

Hi Esben,

thanks for the patch.

Would you consider current converting into YAML format?

Am Donnerstag, 30. Mai 2024, 16:22:54 CEST schrieb Esben Haabendal:
> The LS1021A contains a QUICC Engine Block, so add a node to device
> tree describing that.
> 
> Signed-off-by: Esben Haabendal <esben@...nix.com>
> ---
>  arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 51 +++++++++++++++++++++++++++++++++++
>  1 file changed, 51 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi
> index e86998ca77d6..ff7be69acdd5 100644
> --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi
> @@ -460,6 +460,57 @@ gpio3: gpio@...0000 {
>  			#interrupt-cells = <2>;
>  		};
>  
> +		uqe: uqe@...0000 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			device_type = "qe";
> +			compatible = "fsl,qe", "simple-bus";
> +			ranges = <0x0 0x0 0x2400000 0x40000>;
> +			reg = <0x0 0x2400000 0x0 0x480>;

Properties please in this order:
* compatible
* reg
* #address-cells
* #size-cells
* ranges
* device_type

> +			brg-frequency = <150000000>;
> +			bus-frequency = <300000000>;

Mh, aren't these values depending on your actual RCW configuration?

> +			fsl,qe-num-riscs = <1>;
> +			fsl,qe-num-snums = <28>;

Current bindings defines:
> fsl,qe-snums: This property has to be specified as '/bits/ 8' value,
>   defining the array of serial number (SNUM) values for the virtual
>   threads.

So '/bits/ 8' is missing.

> +			qeic: qeic@80 {
> +				compatible = "fsl,qe-ic";
> +				reg = <0x80 0x80>;
> +				#address-cells = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
> +					      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			ucc@...0 {
> +				cell-index = <1>;
> +				reg = <0x2000 0x200>;
> +				interrupts = <32>;
> +				interrupt-parent = <&qeic>;

Move cell-index to last position.

> +			};
> +
> +			ucc@...0 {
> +				cell-index = <3>;
> +				reg = <0x2200 0x200>;
> +				interrupts = <34>;
> +				interrupt-parent = <&qeic>;

Same here.

> +			};
> +
> +			muram@...00 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				compatible = "fsl,qe-muram", "fsl,cpm-muram";
> +				ranges = <0x0 0x10000 0x6000>;

Node address but no 'reg' property? I have no idea if this is okay.
Also compatible (and possibly reg) first.

Thanks and best regards.
Alexander

> +				data-only@0 {
> +					compatible = "fsl,qe-muram-data",
> +					"fsl,cpm-muram-data";
> +					reg = <0x0 0x6000>;
> +				};
> +			};
> +		};
> +
>  		lpuart0: serial@...0000 {
>  			compatible = "fsl,ls1021a-lpuart";
>  			reg = <0x0 0x2950000 0x0 0x1000>;
> 
> ---
> base-commit: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
> change-id: 20240530-arm-ls1021a-qe-dts-093381110793
> 
> Best regards,
> 


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