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Message-Id: <20240601093232.52319-1-joswang1221@gmail.com>
Date: Sat, 1 Jun 2024 17:32:32 +0800
From: joswang <joswang1221@...il.com>
To: Thinh.Nguyen@...opsys.com
Cc: gregkh@...uxfoundation.org,
linux-usb@...r.kernel.org,
linux-kernel@...r.kernel.org,
joswang <joswang@...ovo.com>
Subject: [PATCH 2/2] usb: dwc3: core: Workaround for CSR read timeout
From: joswang <joswang@...ovo.com>
DWC31 version 2.00a have an issue that would cause
a CSR read timeout When CSR read coincides with RAM
Clock Gating Entry.
This workaround solution disable Clock Gating, sacrificing
power consumption for normal operation.
Signed-off-by: joswang <joswang@...ovo.com>
---
drivers/usb/dwc3/core.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 3a8fbc2d6b99..1df85c505c9e 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -978,11 +978,22 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc)
*
* STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
* SOF/ITP Mode Used
+ *
+ * WORKAROUND: DWC31 version 2.00a have an issue that would
+ * cause a CSR read timeout When CSR read coincides with RAM
+ * Clock Gating Entry.
+ *
+ * This workaround solution disable Clock Gating, sacrificing
+ * power consumption for normal operation.
*/
if ((dwc->dr_mode == USB_DR_MODE_HOST ||
dwc->dr_mode == USB_DR_MODE_OTG) &&
DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
+ else if ((dwc->dr_mode == USB_DR_MODE_HOST ||
+ dwc->dr_mode == USB_DR_MODE_OTG) &&
+ DWC3_VER_IS(DWC31, 200A))
+ reg |= DWC3_GCTL_DSBLCLKGTNG;
else
reg &= ~DWC3_GCTL_DSBLCLKGTNG;
break;
@@ -992,6 +1003,18 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc)
* will work. Device-mode hibernation is not yet implemented.
*/
reg |= DWC3_GCTL_GBLHIBERNATIONEN;
+
+ /*
+ * WORKAROUND: DWC31 version 2.00a have an issue that would
+ * cause a CSR read timeout When CSR read coincides with RAM
+ * Clock Gating Entry.
+ *
+ * This workaround solution disable Clock Gating, sacrificing
+ * power consumption for normal operation.
+ */
+ if ((dwc->dr_mode == USB_DR_MODE_HOST ||
+ dwc->dr_mode == USB_DR_MODE_OTG) && DWC3_VER_IS(DWC31, 200A))
+ reg |= DWC3_GCTL_DSBLCLKGTNG;
break;
default:
/* nothing */
--
2.17.1
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