linux-kernel - Re: [PATCH v2 1/5] dt-bindings: usb: snps,dwc3: Add 'snps,xhci-write-64-hi-lo-quirk' quirk

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <eb13e81c-2669-4e82-86eb-d61203475962@kernel.org>
Date: Mon, 3 Jun 2024 08:57:16 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Jung Daehwan <dh10.jung@...sung.com>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Thinh Nguyen
 <Thinh.Nguyen@...opsys.com>, Mathias Nyman <mathias.nyman@...el.com>,
 Felipe Balbi <balbi@...nel.org>,
 "open list:USB SUBSYSTEM" <linux-usb@...r.kernel.org>,
 "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
 <devicetree@...r.kernel.org>, open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 1/5] dt-bindings: usb: snps,dwc3: Add
 'snps,xhci-write-64-hi-lo-quirk' quirk

On 03/06/2024 05:03, Jung Daehwan wrote:
> On Fri, May 31, 2024 at 10:10:30AM +0200, Krzysztof Kozlowski wrote:
>> On 31/05/2024 08:07, Daehwan Jung wrote:
>>> Add a new quirk for dwc3 core to support writing high-low order.
>>
>> This does not tell me more. Could be OS property as well... please
>> describe hardware and provide rationale why this is suitable for
>> bindings (also cannot be deduced from compatible).
>>
>>
> 
> Hi,
> 
> I'm sorry I didn't describe it in dt-bindings patches.
> It's described in cover-letter and other patches except in dt-bindings.
> I will add it in next submission.
> 
> I've found out the limitation of Synopsys dwc3 controller. This can work
> on Host mode using xHCI. A Register related to ERST should be written
> high-low order not low-high order. Registers are always written low-high order
> following xHCI spec.(64-bit written is done in each 2 of 32-bit)
> That's why new quirk is needed for workaround. This quirk is used not in
> dwc3 controller itself, but passed to xhci quirk eventually. That's because
> this issue occurs in Host mode using xHCI.
> 

If there is only one register then you should just program it
differently and it does not warrant quirk property.

Best regards,
Krzysztof