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Message-ID: <147d58a6-0cad-47b6-a069-755f835a77e9@ti.com>
Date: Mon, 3 Jun 2024 09:17:43 -0500
From: Andrew Davis <afd@...com>
To: Siddharth Vadapalli <s-vadapalli@...com>, <nm@...com>, <vigneshr@...com>,
<kristo@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <rogerq@...nel.org>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <u-kumar1@...com>,
<danishanwar@...com>, <srk@...com>
Subject: Re: [PATCH v4 6/7] arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe
support
On 6/1/24 7:15 AM, Siddharth Vadapalli wrote:
> J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one
> instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane
> SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller.
>
> Since SERDES and PCIe are not present on AM62P SoC, add the device-tree
> nodes corresponding to them in the J722S SoC specific "k3-j722s-main.dtsi"
> file.
>
> Co-developed-by: Ravi Gunasekaran <r-gunasekaran@...com>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@...com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
> ---
> v3:
> https://lore.kernel.org/r/20240524090514.152727-2-s-vadapalli@ti.com/
> https://lore.kernel.org/r/20240524090514.152727-7-s-vadapalli@ti.com/
> and
> https://lore.kernel.org/r/20240524090514.152727-8-s-vadapalli@ti.com/
> Changes since v3:
> - The k3-j722s-main.dtsi specific changes in the above patches have been
> squashed into this patch.
>
> arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 131 ++++++++++++++++++++++
> 1 file changed, 131 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> index 3ca3f0041956..91489014f09e 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> @@ -4,7 +4,121 @@
> * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> +#include <dt-bindings/phy/phy-cadence.h>
> +#include <dt-bindings/phy/phy-ti.h>
> +
> +/ {
> + serdes_refclk: clk-0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + };
> +};
> +
> &cbass_main {
> + serdes_wiz0: phy@...0000 {
> + compatible = "ti,am64-wiz-10g";
> + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> + num-lanes = <1>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> +
> + assigned-clocks = <&k3_clks 279 1>;
> + assigned-clock-parents = <&k3_clks 279 5>;
> +
> + serdes0: serdes@...0000 {
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x0f000000 0x00010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz0 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 279 1>,
> + <&k3_clks 279 1>,
> + <&k3_clks 279 1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> +
> + status = "disabled"; /* Needs lane config */
Does the other SERDES (serdes1) not need this config? It looks like
it does in the board file.. If so disable it too.
Andrew
> + };
> + };
> +
> + serdes_wiz1: phy@...0000 {
> + compatible = "ti,am64-wiz-10g";
> + ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> + num-lanes = <1>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> +
> + assigned-clocks = <&k3_clks 280 1>;
> + assigned-clock-parents = <&k3_clks 280 5>;
> +
> + serdes1: serdes@...0000 {
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x0f010000 0x00010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz1 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 280 1>,
> + <&k3_clks 280 1>,
> + <&k3_clks 280 1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> + };
> + };
> +
> + pcie0_rc: pcie@...2000 {
> + compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
> + reg = <0x00 0x0f102000 0x00 0x1000>,
> + <0x00 0x0f100000 0x00 0x400>,
> + <0x00 0x0d000000 0x00 0x00800000>,
> + <0x00 0x68000000 0x00 0x00001000>;
> + reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> + ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
> + <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
> + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> + interrupt-names = "link_state";
> + interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
> + device_type = "pci";
> + max-link-speed = <3>;
> + num-lanes = <1>;
> + power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
> + clock-names = "fck", "pcie_refclk";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x0 0xff>;
> + vendor-id = <0x104c>;
> + device-id = <0xb010>;
> + cdns,no-bar-match-nbits = <64>;
> + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
> + msi-map = <0x0 &gic_its 0x0 0x10000>;
> + status = "disabled";
> + };
> +
> usbss1: usb@...0000 {
> compatible = "ti,j721e-usb";
> reg = <0x00 0x0f920000 0x00 0x100>;
> @@ -37,3 +151,20 @@ usb1: usb@...00000{
> };
> };
> };
> +
> +&main_conf {
> + serdes_ln_ctrl: mux-controller@...0 {
> + compatible = "reg-mux";
> + reg = <0x4080 0x14>;
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
> + <0x10 0x3>; /* SERDES1 lane0 select */
> + };
> +};
> +
> +&wkup_conf {
> + pcie0_ctrl: pcie0-ctrl@...0 {
> + compatible = "ti,j784s4-pcie-ctrl", "syscon";
> + reg = <0x4070 0x4>;
> + };
> +};
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