linux-kernel - Re: [PATCH 2/2] arm64: dts: qcom: x1e80100: Make the PCIe 6a PHY support 4 lanes mode

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Date: Tue, 4 Jun 2024 14:00:10 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Johan Hovold <johan@...nel.org>, Abel Vesa <abel.vesa@...aro.org>
Cc: Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Rajendra Nayak <quic_rjendra@...cinc.com>,
 Sibi Sankar <quic_sibis@...cinc.com>, linux-arm-msm@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: qcom: x1e80100: Make the PCIe 6a PHY
 support 4 lanes mode



On 6/3/24 14:52, Johan Hovold wrote:

[...]

> 
> As I just mentioned in my reply on the PHY patch, this does not seem to
> work on the CRD were the link still come up as 2-lane (also with the
> clocks fixed):
> 
> 	qcom-pcie 1bf8000.pci: PCIe Gen.4 x2 link up
> 
> So something appears to be wrong here or in the PHY changes.

Is the device on the other end x4-capable? Or does it not matter in
this log line?

Konrad