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Message-ID:
<SG2PR01MB42184CFE2C3D3E210CC6F7DAD7F82@SG2PR01MB4218.apcprd01.prod.exchangelabs.com>
Date: Tue, 4 Jun 2024 12:54:20 +0000
From: Haylen Chu <heylenay@...look.com>
To: "Rafael J. Wysocki" <rafael@...nel.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Zhang Rui <rui.zhang@...el.com>,
Lukasz Luba <lukasz.luba@....com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Chen Wang <unicorn_wang@...look.com>,
Inochi Amaoto <inochiama@...look.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Jisheng Zhang <jszhang@...nel.org>
Cc: linux-pm@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org,
Haylen Chu <heylenay@...look.com>
Subject: [PATCH v2 2/3] riscv: dts: sophgo: cv18xx: Add sensor device and thermal zone
Add common sensor device Sophgo CV18xx SoCs and thermal zone for
CV1800b SoCs.
Signed-off-by: Haylen Chu <heylenay@...look.com>
---
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 30 +++++++++++++++++++++++++
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 8 +++++++
2 files changed, 38 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index ec9530972ae2..9e669ab35380 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -12,6 +12,34 @@ memory@...00000 {
device_type = "memory";
reg = <0x80000000 0x4000000>;
};
+
+ thermal-zones {
+ soc-thermal-0 {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+ thermal-sensors = <&soc_temp>;
+
+ trips {
+ soc_passive: soc-passive {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ soc_hot: soc-hot {
+ temperature = <85000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ soc_critical: soc-critical {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
&plic {
@@ -25,3 +53,5 @@ &clint {
&clk {
compatible = "sophgo,cv1800-clk";
};
+
+
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 891932ae470f..b165866d4cad 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -310,5 +310,13 @@ clint: timer@...00000 {
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
+
+ soc_temp: thermal-sensor@...0000 {
+ compatible = "sophgo,cv180x-thermal";
+ reg = <0x30e0000 0x100>;
+ clocks = <&clk CLK_TEMPSEN>;
+ clock-names = "clk_tempsen";
+ #thermal-sensor-cells = <0>;
+ };
};
};
--
2.45.2
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