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Message-ID: <20240605205658.184399-1-samuel.holland@sifive.com> Date: Wed, 5 Jun 2024 13:56:44 -0700 From: Samuel Holland <samuel.holland@...ive.com> To: linux-riscv@...ts.infradead.org, Palmer Dabbelt <palmer@...belt.com> Cc: Andrew Jones <ajones@...tanamicro.com>, Conor Dooley <conor@...nel.org>, linux-kernel@...r.kernel.org, Deepak Gupta <debug@...osinc.com>, Samuel Holland <samuel.holland@...ive.com> Subject: [PATCH 0/3] riscv: Per-thread envcfg CSR support This series (or equivalent) is a prerequisite for both user-mode pointer masking and CFI support, as those are per-thread features are controlled by fields in the envcfg CSR. These patches are based on v1 of the pointer masking series[1], with significant input from both Deepak and Andrew. By sending this as a separate series, hopefully we can converge on a single implementation of this functionality. [1]: https://lore.kernel.org/linux-riscv/20240319215915.832127-6-samuel.holland@sifive.com/ Samuel Holland (3): riscv: Enable cbo.zero only when all harts support Zicboz riscv: Add support for per-thread envcfg CSR values riscv: Call riscv_user_isa_enable() only on the boot hart arch/riscv/include/asm/cpufeature.h | 2 +- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/switch_to.h | 8 ++++++++ arch/riscv/kernel/cpufeature.c | 13 +++++++++---- arch/riscv/kernel/smpboot.c | 2 -- arch/riscv/kernel/suspend.c | 4 ++-- 6 files changed, 21 insertions(+), 9 deletions(-) -- 2.44.1
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