linux-kernel - Re: [PATCH] clk: qcom: gcc-sm8450: set OPS_PARENT_ENABLE on gcc_sdcc2_apps_clk

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Message-ID: <93eb11e7-21d7-4d3b-b033-b66898ea7874@linaro.org>
Date: Thu, 6 Jun 2024 13:56:25 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Stephen Boyd <sboyd@...nel.org>, Bjorn Andersson <andersson@...nel.org>,
 Michael Turquette <mturquette@...libre.com>, Vinod Koul <vkoul@...nel.org>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
 linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
 linux-kernel@...r.kernel.org, Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Subject: Re: [PATCH] clk: qcom: gcc-sm8450: set OPS_PARENT_ENABLE on
 gcc_sdcc2_apps_clk_src

On 7.05.2024 11:52 PM, Stephen Boyd wrote:
> Quoting Konrad Dybcio (2024-05-07 14:17:01)
>>
>>
>> On 5/7/24 22:28, Stephen Boyd wrote:
>>>>
>>>
>>> Can you share your patch that prints the message? What bit are you
>>> checking in the hardware to determine if the RCG is enabled? Do you also
>>> print the enable count in software?
>>
>> I already reset-ed the tree state, but I added something like
>>
>> if (rcg->cmd_rcgr == the one in the declaration)
>>         pr_err("gcc_sdcc2_apps_clk_src is %s\n", clk_is_enabled(hw) ? "ENABLED" : "DISABLED");
>>
>> to drivers/clk/qcom/clk-rcg2.c : __clk_rcg2_set_rate()
>>
>>
> 
> Ok. You're reading the software state because there isn't an is_enabled
> clk_op for RCGs. Can you also read the CMD register (0x0 offset from
> base) and check for CMD_ROOT_EN (bit 1) being set? That's what I mean
> when I'm talking about the RCG being enabled in hardware. Similarly,
> read CMD_ROOT_OFF (bit 31) to see if some child branch of the RCG is
> enabled at this time.

[    3.998362] gcc_sdcc2_apps_clk_src is SW-DISABLED, CMD_ROOT_EN=0 CMD_ROOT_OFF=1
[    3.999896] scsi host0: ufshcd
[    4.006712] ------------[ cut here ]------------
[    4.013751] gcc_sdcc2_apps_clk_src: rcg didn't update its configuration.

[...]

[    4.288626] gcc_sdcc2_apps_clk_src is SW-ENABLED, CMD_ROOT_EN=0 CMD_ROOT_OFF=0


Code:

diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 9b3aaa7f20ac..a24b8931d7a1 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -471,6 +471,12 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
        const struct freq_tbl *f;
 
+       if (rcg->cmd_rcgr == 0x24014)
+               pr_err("gcc_sdcc2_apps_clk_src is SW-%s, CMD_ROOT_EN=%u CMD_ROOT_OFF=%u\n",
+                      clk_hw_is_enabled(hw) ? "ENABLED" : "DISABLED",
+                      regmap_test_bits(rcg->clkr.regmap, 0x24014 + CMD_REG, CMD_ROOT_EN),
+                      regmap_test_bits(rcg->clkr.regmap, 0x24014 + CMD_REG, CMD_ROOT_OFF));
+
        switch (policy) {
        case FLOOR:
                f = qcom_find_freq_floor(rcg->freq_tbl, rate);

Konrad