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Message-ID: <ef3f942c1d933ef757a0de84c2890d6779471239.1717755404.git.shravankr@nvidia.com>
Date: Fri, 7 Jun 2024 06:21:14 -0400
From: Shravan Kumar Ramani <shravankr@...dia.com>
To: Hans de Goede <hdegoede@...hat.com>, Ilpo Jarvinen
<ilpo.jarvinen@...ux.intel.com>, Vadim Pasternak <vadimp@...dia.com>, "David
Thompson" <davthompson@...dia.com>
CC: Shravan Kumar Ramani <shravankr@...dia.com>,
<platform-driver-x86@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH v3 4/4] Documentation/ABI: Add new sysfs fields to sysfs-platform-mellanox-pmc
Document newly added "count_clock" and "use_odd_counter" sysfs entries
for the Mellanox BlueField PMC driver.
Signed-off-by: Shravan Kumar Ramani <shravankr@...dia.com>
Reviewed-by: David Thompson <davthompson@...dia.com>
---
.../ABI/testing/sysfs-platform-mellanox-pmc | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-platform-mellanox-pmc b/Documentation/ABI/testing/sysfs-platform-mellanox-pmc
index 9f987c6410da..ee03d066c0d9 100644
--- a/Documentation/ABI/testing/sysfs-platform-mellanox-pmc
+++ b/Documentation/ABI/testing/sysfs-platform-mellanox-pmc
@@ -52,3 +52,26 @@ Description:
Writing 0 to the sysfs will clear the counter, writing any other
value is not allowed.
+What: /sys/bus/platform/devices/<HID>/hwmon/hwmonX/<block>/count_clock
+Date: May 2024
+KernelVersion: 6.10
+Contact: "Shravan Kumar Ramani <shravankr@...dia.com>"
+Description:
+ Use a counter for counting cycles. This is used to repurpose/dedicate
+ any of the counters in the block to counting cycles. Each counter is
+ represented by a bit (bit 0 for counter0, bit1 for counter1 and so on)
+ and setting the corresponding bit will reserve that specific counter
+ for counting cycles and override the event<N> setting.
+
+What: /sys/bus/platform/devices/<HID>/hwmon/hwmonX/<block>/use_odd_counter
+Date: May 2024
+KernelVersion: 6.10
+Contact: "Shravan Kumar Ramani <shravankr@...dia.com>"
+Description:
+ Form 64-bit counter using 2 32-bit counters. This is used to combine
+ 2 adjacent counters to form a single 64-bit counter. Each even counter
+ is represented by a bit and setting the bit will join the corresponding
+ even counter with the next (odd) counter. The full 64-bit value can be
+ accessed using the same 2 counter<N> and counter<N+1> sysfs, with each
+ of them holding the lower and upper 32 bits respectively.
+
--
2.30.1
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