[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20240607133347.3291040-4-peng.fan@oss.nxp.com>
Date: Fri, 7 Jun 2024 21:33:35 +0800
From: "Peng Fan (OSS)" <peng.fan@....nxp.com>
To: abelvesa@...nel.org,
mturquette@...libre.com,
sboyd@...nel.org,
shawnguo@...nel.org,
s.hauer@...gutronix.de,
kernel@...gutronix.de,
festevam@...il.com
Cc: imx@...ts.linux.dev,
linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Ye Li <ye.li@....com>,
Peng Fan <peng.fan@....com>
Subject: [PATCH V3 03/15] clk: imx: composite-7ulp: Check the PCC present bit
From: Ye Li <ye.li@....com>
When some module is disabled by fuse, its PCC PR bit is default 0 and
PCC is not operational. Any write to this PCC will cause SError.
Fixes: b40ba8065347 ("clk: imx: Update the compsite driver to support imx8ulp")
Reviewed-by: Peng Fan <peng.fan@....com>
Signed-off-by: Ye Li <ye.li@....com>
Signed-off-by: Peng Fan <peng.fan@....com>
---
drivers/clk/imx/clk-composite-7ulp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c
index e208ddc51133..db7f40b07d1a 100644
--- a/drivers/clk/imx/clk-composite-7ulp.c
+++ b/drivers/clk/imx/clk-composite-7ulp.c
@@ -14,6 +14,7 @@
#include "../clk-fractional-divider.h"
#include "clk.h"
+#define PCG_PR_MASK BIT(31)
#define PCG_PCS_SHIFT 24
#define PCG_PCS_MASK 0x7
#define PCG_CGC_SHIFT 30
@@ -78,6 +79,12 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name,
struct clk_hw *hw;
u32 val;
+ val = readl(reg);
+ if (!(val & PCG_PR_MASK)) {
+ pr_info("PCC PR is 0 for clk:%s, bypass\n", name);
+ return 0;
+ }
+
if (mux_present) {
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
--
2.37.1
Powered by blists - more mailing lists