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Message-ID: <3221526e-8698-4930-81e6-715cf3f1a18f@amd.com>
Date: Mon, 10 Jun 2024 15:00:24 -0500
From: Wei Huang <wei.huang2@....com>
To: Jonathan Cameron <Jonathan.Cameron@...wei.com>
Cc: linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-doc@...r.kernel.org, netdev@...r.kernel.org, bhelgaas@...gle.com,
 corbet@....net, davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
 pabeni@...hat.com, alex.williamson@...hat.com, gospo@...adcom.com,
 michael.chan@...adcom.com, ajit.khaparde@...adcom.com,
 somnath.kotur@...adcom.com, andrew.gospodarek@...adcom.com,
 manoj.panicker2@....com, Eric.VanTassell@....com, vadim.fedorenko@...ux.dev,
 horms@...nel.org, bagasdotme@...il.com
Subject: Re: [PATCH V2 2/9] PCI: Add TPH related register definition



On 6/7/24 11:17, Jonathan Cameron wrote:
> On Fri, 31 May 2024 16:38:34 -0500
> Wei Huang <wei.huang2@....com> wrote:
>>  /* TPH Requester */
>>  #define PCI_TPH_CAP		4	/* capability register */
>> +#define  PCI_TPH_CAP_NO_ST	0x1	/* no ST mode supported */
>> +#define  PCI_TPH_CAP_NO_ST_SHIFT	0x0	/* no ST mode supported shift */
>> +#define  PCI_TPH_CAP_INT_VEC	0x2	/* interrupt vector mode supported */
>> +#define  PCI_TPH_CAP_INT_VEC_SHIFT	0x1	/* interrupt vector mode supported shift */
>> +#define  PCI_TPH_CAP_DS		0x4	/* device specific mode supported */
>> +#define  PCI_TPH_CAP_DS_SHIFT	0x4	/* device specific mode supported shift */
>>  #define  PCI_TPH_CAP_LOC_MASK	0x600	/* location mask */
>> -#define   PCI_TPH_LOC_NONE	0x000	/* no location */
>> -#define   PCI_TPH_LOC_CAP	0x200	/* in capability */
>> -#define   PCI_TPH_LOC_MSIX	0x400	/* in MSI-X */
> 
> It's a userspace header, relatively unlikely to be safe to change it...
> This would also be inconsistent with how some other registers are defined in here.
> 
> I'd love it if we could tidy this up, but we are stuck by this being
> in uapi.

Alex Williamson had a similar comment in another email. In V3, I will
only add (necessary) new definitions and refrain from touching the
existing ones.


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