linux-kernel - Re: [PATCH v7 6/7] iommu/riscv: Command and fault queue support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date: Mon, 10 Jun 2024 14:11:23 -0700
From: Tomasz Jeznach <tjeznach@...osinc.com>
To: Andrew Jones <ajones@...tanamicro.com>
Cc: Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>, 
	Robin Murphy <robin.murphy@....com>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Anup Patel <apatel@...tanamicro.com>, Sunil V L <sunilvl@...tanamicro.com>, 
	Nick Kossifidis <mick@....forth.gr>, Sebastien Boeuf <seb@...osinc.com>, Rob Herring <robh+dt@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, devicetree@...r.kernel.org, 
	iommu@...ts.linux.dev, linux-riscv@...ts.infradead.org, 
	linux-kernel@...r.kernel.org, linux@...osinc.com, 
	Lu Baolu <baolu.lu@...ux.intel.com>, Zong Li <zong.li@...ive.com>
Subject: Re: [PATCH v7 6/7] iommu/riscv: Command and fault queue support

On Mon, Jun 10, 2024 at 4:06 AM Andrew Jones <ajones@...tanamicro.com> wrote:
>
> On Wed, Jun 05, 2024 at 12:57:48PM GMT, Tomasz Jeznach wrote:
> ...
> > +static int riscv_iommu_queue_alloc(struct riscv_iommu_device *iommu,
> > +                                struct riscv_iommu_queue *queue,
> > +                                size_t entry_size)
> > +{
> > +     unsigned int logsz;
> > +     u64 qb, rb;
> > +
> > +     /*
> > +      * Use WARL base register property to discover maximum allowed
> > +      * number of entries and optional fixed IO address for queue location.
> > +      */
> > +     riscv_iommu_writeq(iommu, queue->qbr, RISCV_IOMMU_QUEUE_LOG2SZ_FIELD);
> > +     qb = riscv_iommu_readq(iommu, queue->qbr);
> > +
> > +     /*
> > +      * Calculate and verify hardware supported queue length, as reported
> > +      * by the field LOG2SZ, where max queue length is equal to 2^(LOG2SZ + 1).
> > +      * Update queue size based on hardware supported value.
> > +      */
> > +     logsz = ilog2(queue->mask);
> > +     if (logsz > FIELD_GET(RISCV_IOMMU_QUEUE_LOG2SZ_FIELD, qb))
> > +             logsz = FIELD_GET(RISCV_IOMMU_QUEUE_LOG2SZ_FIELD, qb);
> > +
> > +     /*
> > +      * Use WARL base register property to discover an optional fixed IO
> > +      * address for queue ring buffer location. Otherwise allocate contiguous
> > +      * system memory.
> > +      */
> > +     if (FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb)) {
> > +             const size_t queue_size = entry_size << (logsz + 1);
> > +
> > +             queue->phys = ppn_to_phys(FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb));
>
> Shouldn't this be something like
>
>   FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb) << PAGE_SHIFT
>
> ppn_to_phys() assumes the ppn it's converting to be shifted up by 10, but
> FIELD_GET has shifted it down to zero.
>

Good catch. It should be pfn_to_phys(). Fixed & verified on IOMMU with
queue ring buffers in fixed memory location.

Thanks,
- Tomasz

> Thanks,
> drew