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Message-Id: <20240610233221.242749-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Tue, 11 Jun 2024 00:32:17 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Magnus Damm <magnus.damm@...il.com>
Cc: linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [RFC PATCH v2 0/4] Add CPG support for RZ/V2H(P) SoC
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Hi All,
This patch series aims to add the CPG support for the Renesas
RZ/V2H(P) SoC.
Im sending this as an RFC as I have dropped the module clk macros to
avoid adding reserved macros and instead now using the combination of
register index and bits as unique number for clks and resets.
v1->RFC v2
- Updated commit message
- Updated description for binding as suggested by Geert
- Updated descriptions for clocks and resets property
- Renamed extal->qextal
- Updated '#power-domain-cells' value
- Dropped the module clocks and just added the core clocks
- Introduced family specific config option
- Now using register indexes for CLKON/CLKMON/RST/RSTMON
- Introduced PLL_CONF macro
- Dropped function pointer to get PLL_CLK1/2 offsets
- Added range check for core clks
- Dropped NULLified clocks check
- Dropped pll_clk1/clk2_offset
- Made r9a09g057_mod_clks/r9a09g057_resets as static const
v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240524082800.333991-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
Lad Prabhakar (4):
dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
dt-bindings: clock: Add R9A09G057 core clocks
clk: renesas: Add family-specific clock driver for RZ/V2H(P)
clk: renesas: Add RZ/V2H(P) CPG driver
.../bindings/clock/renesas,rzv2h-cpg.yaml | 81 +++
drivers/clk/renesas/Kconfig | 9 +
drivers/clk/renesas/Makefile | 2 +
drivers/clk/renesas/r9a09g057-cpg.c | 77 ++
drivers/clk/renesas/rzv2h-cpg.c | 676 ++++++++++++++++++
drivers/clk/renesas/rzv2h-cpg.h | 164 +++++
include/dt-bindings/clock/r9a09g057-cpg.h | 21 +
7 files changed, 1030 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
create mode 100644 drivers/clk/renesas/r9a09g057-cpg.c
create mode 100644 drivers/clk/renesas/rzv2h-cpg.c
create mode 100644 drivers/clk/renesas/rzv2h-cpg.h
create mode 100644 include/dt-bindings/clock/r9a09g057-cpg.h
--
2.34.1
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