linux-kernel - Re: [PATCH 2/2] PCI: microchip: Fix inbound address translation tables

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Message-ID: <20240610-pointless-hamstring-908149945428@wendy>
Date: Mon, 10 Jun 2024 10:44:54 +0100
From: Conor Dooley <conor.dooley@...rochip.com>
To: Daire McNamara <daire.mcnamara@...rochip.com>
CC: <linux-pci@...r.kernel.org>, Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof Wilczyński <kw@...ux.com>, Rob Herring
	<robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
	<linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH 2/2] PCI: microchip: Fix inbound address translation
 tables

On Fri, May 31, 2024 at 09:53:33AM +0100, Daire McNamara wrote:
> On Microchip PolarFire SoC the PCIe Root Port can be behind one of three
> general purpose Fabric Interface Controller (FIC) buses that encapsulates
> an AXI-S bus. Depending on which FIC(s) the Root Port is connected
> through to CPU space, and what address translation is done by that FIC,
> the Root Port driver's inbound address translation may vary.
> 
> For all current supported designs and all future expected designs,
> inbound address translation done by a FIC on PolarFire SoC varies
> depending on whether PolarFire SoC in operating in dma-coherent mode or
> dma-noncoherent mode.
> 
> The setup of the outbound address translation tables in the root port
> driver only needs to handle these two cases.
> 
> Setup the inbound address translation tables to one of two address
> translations, depending on whether the rootport is marked as dma-coherent or
> dma-noncoherent.

Since we're talking about dma-noncoherent here, I think this series
should contain a patch that adds the property to the binding for PCIe:

-- >8 --

From af066543b8f8b8b0b37e0844979f0c3e28f30513 Mon Sep 17 00:00:00 2001
From: Conor Dooley <conor.dooley@...rochip.com>
Date: Mon, 20 Mar 2023 11:02:11 +0000
Subject: [PATCH] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent

PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.

Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
 Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index 45c14b6e4aa4..2f21109c3580 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -53,6 +53,8 @@ properties:
     items:
       pattern: '^fic[0-3]$'
 
+  dma-noncoherent: true
+
   interrupts:
     minItems: 1
     items:
-- 
2.43.2



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