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Message-Id: <20240609-support_vendor_extensions-v2-0-9a43f1fdcbb9@rivosinc.com>
Date: Sun, 09 Jun 2024 21:34:13 -0700
From: Charlie Jenkins <charlie@...osinc.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Conor Dooley <conor.dooley@...rochip.com>, Evan Green <evan@...osinc.com>,
Andy Chiu <andy.chiu@...ive.com>
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Charlie Jenkins <charlie@...osinc.com>
Subject: [PATCH v2 0/4] riscv: Separate vendor extensions from standard
extensions
All extensions, both standard and vendor, live in one struct
"riscv_isa_ext". There is currently one vendor extension, xandespmu, but
it is likely that more vendor extensions will be added to the kernel in
the future. As more vendor extensions (and standard extensions) are
added, riscv_isa_ext will become more bloated with a mix of vendor and
standard extensions.
This also allows each vendor to be conditionally enabled through
Kconfig.
---
This has been split out from the previous series that contained the
addition of xtheadvector due to lack of reviews. The xtheadvector
support will be posted again separately from this.
The reviewed-bys on "riscv: Extend cpufeature.c to detect vendor extensions"
and "riscv: Introduce vendor variants of extension helpers" have been
dropped in this series. The majority of the code is the same in these
patches, but thead-specific code is swapped out with andes-specific
code. The changes are minimal, but I decided to drop the reviews in case
I inadvertently introduced issues.
The alternative patching code from "riscv: Introduce vendor variants of
extension helpers" has been migrated to "riscv: Extend cpufeature.c to
detect vendor extensions" such that the andes patching still works in
that patch.
I also fix a bug in this patch from the previous series that the Andes
extensions were not being properly enabled due to the manual alternative
patching not incrementing the id to be greater than
RISCV_VENDOR_EXT_ALTERNATIVES_BASE.
To: Paul Walmsley <paul.walmsley@...ive.com>
To: Palmer Dabbelt <palmer@...belt.com>
To: Albert Ou <aou@...s.berkeley.edu>
To: Conor Dooley <conor.dooley@...rochip.com>
To: Evan Green <evan@...osinc.com>
To: Andy Chiu <andy.chiu@...ive.com>
Cc: linux-riscv@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org
Signed-off-by: Charlie Jenkins <charlie@...osinc.com>
---
Changes in v2:
- Fixed issue in riscv_fill_vendor_ext_list() that initalizion was only
happening properly for the first vendor. Add is_initialized field to
riscv_isa_vendor_ext_data_list to allow intialization to be tracked on
a per-vendor basis.
- Link to v1: https://lore.kernel.org/r/20240515-support_vendor_extensions-v1-0-b05dd5ea7d8d@rivosinc.com
---
Charlie Jenkins (4):
riscv: Extend cpufeature.c to detect vendor extensions
riscv: Add vendor extensions to /proc/cpuinfo
riscv: Introduce vendor variants of extension helpers
riscv: cpufeature: Extract common elements from extension checking
arch/riscv/Kconfig | 2 +
arch/riscv/Kconfig.vendor | 19 ++++
arch/riscv/errata/andes/errata.c | 3 +
arch/riscv/errata/sifive/errata.c | 3 +
arch/riscv/errata/thead/errata.c | 3 +
arch/riscv/include/asm/cpufeature.h | 96 ++++++++++------
arch/riscv/include/asm/hwcap.h | 1 -
arch/riscv/include/asm/vendor_extensions.h | 104 +++++++++++++++++
arch/riscv/include/asm/vendor_extensions/andes.h | 19 ++++
arch/riscv/kernel/Makefile | 2 +
arch/riscv/kernel/cpu.c | 35 +++++-
arch/riscv/kernel/cpufeature.c | 137 +++++++++++++++++------
arch/riscv/kernel/vendor_extensions.c | 56 +++++++++
arch/riscv/kernel/vendor_extensions/Makefile | 3 +
arch/riscv/kernel/vendor_extensions/andes.c | 18 +++
drivers/perf/riscv_pmu_sbi.c | 11 +-
16 files changed, 438 insertions(+), 74 deletions(-)
---
base-commit: c3f38fa61af77b49866b006939479069cd451173
change-id: 20240515-support_vendor_extensions-aa80120e4230
--
- Charlie
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